NDLI: The performance advantages of integrating block data transfer in cache-coherent multiprocessors

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The performance advantages of integrating block data transfer in cache-coherent multiprocessors

Content Provider	ACM Digital Library
Author	Singh, Jaswinder Pal Woo, Steven Cameron Hennessy, John L.
Abstract	Integrating support for block data transfer has become an important emphasis in recent cache-coherent shared address space multiprocessors. This paper examines the potential performance benefits of adding this support. A set of ambitious hardware mechanisms is used to study performance gains in five important scientific computations that appear to be good candidates for using block transfer. Our conclusion is that the benefits of block transfer are not substantial for hardware cache-coherent multiprocessors. The main reasons for this are (i) the relatively modest fraction of time applications spend in communication amenable to block transfer, (ii) the difficulty of finding enough independent computation to overlap with the communication latency that remains after block transfer, and (iii) long cache lines often capture many of the benefits of block transfer in efficient cache-coherent machines. In the cases where block transfer improves performance, prefetching can often provide comparable, if not superior, performance benefits. We also examine the impact of varying important communication parameters and processor speed on the effectiveness of block transfer, and comment on useful features that a block transfer facility should support for real applications.
Starting Page	219
Ending Page	229
Page Count	11
File Format	PDF
ISBN	0897916603
DOI	10.1145/195473.195547
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1994-11-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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