NDLI: Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing

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Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing

Content Provider	ACM Digital Library
Author	El-Araby, Esam Gonzalez, Ivan El-Ghazawi, Tarek
Abstract	High-Performance Reconfigurable Computing (HPRC) systems have always been characterized by their high performance and flexibility. Flexibility has been traditionally exploited through the Run-Time Reconfiguration (RTR) provided by most of the available platforms. However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Run-Time Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the state-of-the-art HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.
Starting Page	11
Ending Page	20
Page Count	10
File Format	PDF
ISBN	9781595938947
DOI	10.1145/1328554.1328561
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-11-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	High performance computing Field programmable gate arrays (fpga) Reconfigurable computing Dynamic partial reconfiguration
Content Type	Text
Resource Type	Article

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