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The performance enhancement of a run-time reconfigurable fpga system through partial reconfiguration (1995).
| Content Provider | CiteSeerX |
|---|---|
| Author | Hadley, James D. |
| Abstract | Partial reconfiguration is the ability of certain Field Programmable Gate Arrays (FPGAs) to reconfigure only selected portions of their programmable hardware while other portions continue to operate undisturbed. The RRANN2 system, described in this thesis, was developed and built by the author specifically to demonstrate that partial reconfiguration can increase the performance of a runtime reconfigurable system. Implementing an artificial neural network, RRANN2 carefully organizes its FPGA configurations in order to establish a large number of functional and physical commonalities between each circuit design. By leaving common circuitry resident on the FPGA during system reconfiguration, RRANN2 successfully reduced its reconfiguration overhead by 53.4%. For smaller neural network applications, where reconfiguration time is the most dominant factor in the system's execution time, this resulted in a 100% increase in system performance. Before partial reconfiguration is feasible for most... |
| File Format | |
| Publisher Date | 1995-01-01 |
| Access Restriction | Open |
| Subject Keyword | Partial Reconfiguration Run-time Reconfigurable Fpga System Performance Enhancement Runtime Reconfigurable System System Reconfiguration Rrann2 System Artificial Neural Network Physical Commonality Fpga Configuration Programmable Hardware Execution Time Dominant Factor Neural Network Application Large Number Common Circuitry Resident Certain Field Programmable Gate Array System Performance Reconfiguration Overhead Reconfiguration Time Circuit Design |
| Content Type | Text |
