NDLI: Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

Issue 4, January 2009

Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms

FPGA Acceleration of RankBoost in Web Search Engines

Searching for Transient Pulses with the ETA Radio Telescope

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

RAT: RC Amenability Test for Rapid Performance Prediction

Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs

Issue 3, September 2008

Issue 2, June 2008

Issue 1(Special edition on the 15th international symposium on FPGAs), March 2008

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

Content Provider	ACM Digital Library
Author	Gonzalez, Ivan El-araby, Esam El-ghazawi, Tarek
Copyright Year	2009
Abstract	Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.
Starting Page	1
Ending Page	23
Page Count	23
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/1462586.1462590
Volume Number	1
Issue Number	4
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	High performance computing Dynamic partial reconfiguration Field programmable gate arrays (FPGA) Reconfigurable computing
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing

Virtualizing and sharing reconfigurable resources in High-Performance Reconfigurable Computing systems

Performance of partial reconfiguration in FPGA systems: A survey and a cost model

Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications

High performance reconfigurable multi-processor-based computing on FPGAs

Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration

An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

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