NDLI: A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator

Please wait, while we are loading the content...

Innovation for Future Connected Compute

Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ

TeleProbe: Zero-power Contactless Probing for Implantable Medical Devices

Energy-Efficient Adaptive Classifier Design for Mobile Systems

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study

Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor

SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs

Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs

Extending the Moore's law by exploring new data center architecture: Invited Paper

On Effective and Efficient Quality Management for Approximate Computing

Unified Power Frequency Model Framework

Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming

DynSleep: Fine-grained Power Management for a Latency-Critical Data Center Application

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency

Reducing Power Consumption of GPGPUs Through Instruction Reordering

Coordinating Communication, Technology and Design in the IOT Era

Ferroelectric Transistor based Non-Volatile Flip-Flop

SocialHBC: Social Networking and Secure Authentication using Interference-Robust Human Body Communication

Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs

Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip

DeLight: Adding Energy Dimension To Deep Neural Networks

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Heterogeneous Computing and Infrastructure for Energy Efficiency in Microsoft Data Centers: Extended Abstract

ACAM: Approximate Computing Based on Adaptive Associative Memory with Online Learning

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors

An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor Platforms

HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency Capping Governor for Energy-Efficient Mobile Gaming

Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells

Design and implementation of nonvolatile power-gating SRAM using SOTB technology

A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques

Terahertz Technology and its Applications: Is it All Hype?

Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures

A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off

A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs

Analysis and Design of Energy Efficient Time Domain Signal Processing

A Light-powered, "Always-On", Smart Camera with Compressed Domain Gesture Detection

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper

Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network Hardware

Overview of IEEE1801-2015: Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems: Invited Paper

Bit Serializing a Microprocessor for Ultra-low-power

Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation

T-DVS: Temperature-aware DVS based on Temperature Inversion Phenomenon

An Efficient Parallel Scheduling Scheme on Multi-partition PCM Architecture

Power--Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems

Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design

An Energy-Efficient Computational Model for Uncertainty Management in Dynamically Changing Networked Wearables

An Energy-Efficient PUF Design: Computing While Racing

Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper

A Programmable Analog-to-Information Converter for Agile Biosensing

Therma: Thermal-aware Run-time Thread Migration for Nanophotonic Interconnects

Enhancing DRAM Self-Refresh for Idle Power Reduction

In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches

FVCAG: A framework for formal verification driven power modeling and verification

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization

A 386-μW, 15.2-bit Programmable-Gain Embedded Delta-Sigma ADC for Sensor Applications

Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency

A Thermal-Aware Physical Space Allocation Strategy for 3D Flash Memory Storage Systems

OS-based Resource Accounting for Asynchronous Resource Use in Mobile Systems

Dynamic Voltage Scaling Using Scene Change Detection for Video Playback on Mobile AMOLED Displays

Can We Guarantee Performance Requirements under Workload and Process Variations?

A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions

Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster

A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator

Content Provider	ACM Digital Library
Author	He, Zhezhi Fan, Deliang
Abstract	Current-mode Analog-to-Digital Converter (ADC) has drawn many attentions due to its high operating speed, power and ground noise immunity, and etc. However, 2n -- 1 comparators are required in traditional n-bit current-mode ADC design, leading to inevitable high power consumption and large chip area. In this work, we propose a low power and compact current mode Multi-Threshold Comparator (MTC) based on giant Spin Hall Effect (SHE). The two threshold currents of the proposed SHE-MTC are 200μA and 250μA with 1ns switching time, respectively. The proposed current-mode hybrid spin-CMOS flash ADC based on SHE-MTC reduces the number of comparators almost by half (2n-1), thus correspondingly reducing the required current mirror branches, total power consumption and chip area. Moreover, due to the non-volatility of SHE-MTC, the front-end analog circuits can be switched off when it is not required to further increase power efficiency. The device dynamics of SHE-MTC is simulated using a numerical device model based on Landau-Lifshitz-Gilbert (LLG) equation with Spin-Transfer Torque (STT) term and SHE term. The device-circuit co-simulation in SPICE (45nm CMOS technology) have shown that the average power dissipation of proposed ADC is 1.9mW, operating at 500MS/s with 1.2 V power supply. The INL and DNL are in the range of 0.23LSB and 0.32LSB, respectively.
Starting Page	314
Ending Page	319
Page Count	6
File Format	PDF
ISBN	9781450341851
DOI	10.1145/2934583.2934642
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-08-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Spin hall effect Flash adc Multi-threshold comparator
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in