NDLI: Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs

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Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs

Content Provider	ACM Digital Library
Author	Lim, Sung Kyu Milojevic, Dragomir Raghavan, Praveen Verkest, Diederik Debacker, Peter Ku, Bon Woong Thean, Aaron
Abstract	In this paper, we develop physical design tools and methodologies to tackle the inter-tier performance variations caused by low temperature manufacturing in 2-tier gate-level monolithic 3D ICs (M3D). First, we model the top tier front-end-of-line (FEOL) device mobility degradation and its impact on cell delay/power values. Next, we quantify the impact of tungsten interconnect and cost-driven metal layer saving in the back-end-of-line (BEOL) of the bottom tier. These device and interconnect degradation models are used in our new full-chip M3D physical design flow named Derated 2D. This flow overcomes the well-known drawback of the state-of-the-art Shrunk 2D that requires shrinking of layout objects and RC parasitics. Also, Derated 2D performs low-temperature process-aware tier partitioning to effectively keep timing-critical components in the bottom tier. Moreover, Derated 2D conducts timing-driven monolithic inter-tier via (MIV) planning to cope with the resistivity increase in tungsten BEOL. Lastly, Derated 2D offers an effective timing closure solution through a post-route optimization. Experiments based on a foundry-grade 7nm FinFET process design kit (PDK) show that Derated 2D achieves up to 36% performance improvement and 10% energy saving compared with Shrunk 2D. Using a post-route optimization, Derated 2D further improves timing under various FEOL/BEOL degradation settings at a minimum energy overhead.
Starting Page	76
Ending Page	81
Page Count	6
File Format	PDF
ISBN	9781450341851
DOI	10.1145/2934583.2934622
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-08-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Gate-level monolithic 3d ic Feol/beol degradation Low temperature manufacturing process
Content Type	Text
Resource Type	Article

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