NDLI: Proceedings of the 2006 Asia and South Pacific Design Automation Conference (ASP-DAC '06)

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Automotive electronics: steady growth for years to come!

Challenging device innovation

Effective platform-based development for large-scale systems design

Transition-based coverage estimation for symbolic model checking

Constraint-driven bus matrix synthesis for MPSoC

Robust analytical gate delay modeling for low voltage circuits

A low dynamic power and low leakage power 90-nm CMOS square-root circuit

Energy savings through embedded processing on disk system

SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design

A robust detailed placement for mixed-size IC designs

Electrothermal analysis and optimization techniques for nanoscale integrated circuits

An anytime symmetry detection algorithm for ROBDDs

Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena

Post-routing redundant via insertion for yield/reliability improvement

Current trends in flash memory technology: invited paper

Delay defect screening for a 2.16GHz SPARC64 microprocessor

High-level architecture exploration for MPEG4 encoder with custom parameters

A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings

An introduction to OpenAccess: an open source data model and API for IC design

Depth-driven verification of simultaneous interfaces

Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system

Wire sizing with scattering effect for nanoscale interconnection

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

Reusable component IP design using refinement-based design environment

DraXRouter: global routing in X-Architecture with dynamic resource assignment

A routability constrained scan chain ordering technique for test power reduction

Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation

Statistical corner conditions of interconnect delay (corner LPE specifications)

Introduction to H.264 advanced video coding

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs

Finding optimal L1 cache configuration for embedded systems

Efficient early stage resonance estimation techniques for C4 package

A new test and characterization scheme for 10+ GHz low jitter wide band PLL

TAPHS: thermal-aware unified physical-level and high-level synthesis

Workload prediction and dynamic voltage scaling for MPEG decoding

Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops

Word level functional coverage computation

Improving routing efficiency for network-on-chip through contention-aware input selection

CGTA: current gain-based timing analysis for logic cells

A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits

Energy-aware computation duplication for improving reliability in embedded chip multiprocessors

The design and implementation of a low-latency on-chip network

FastPlace 2.0: an efficient analytical placer for mixed-mode designs

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

High level equivalence symmetric input identification

Newton: a library-based analytical synthesis tool for RF-MEMS resonators

Temperature-aware routing in 3D ICs

Configurability of performance and overheads in flash management

A dynamic test compaction procedure for high-quality path delay testing

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method

An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits

Open access overview "industrial experience"

FSM-based transaction-level functional coverage for interface compliance verification

Optimal TDMA time slot and cycle length allocation for hard real-time systems

Adaptive admittance-based conductor meshing for interconnect analysis

Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise

Analysis and optimization of gate leakage current of power gating circuits

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Diagonal routing in high performance microprocessor design

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles

Speed binning aware design methodology to improve profit under parameter variations

Algorithms and DSP implementation of H.264/AVC

A fixed-die floorplanning algorithm using an analytical approach

Memory size computation for multimedia processing applications

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters

An SPU reference model for simulation, random test generation and verification

An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model

Lazy BTB: reduce BTB energy consumption using dynamic profiling

Parameterized block-based non-gaussian statistical gate timing analysis

Discovering the input assumptions in specification refinement coverage

Physical design implementation of segmented buses to reduce communication energy

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths

A 16-bit, low-power microsystem with monolithic MEMS-LC clocking

Object duplication for improving reliability

A near optimal deblocking filter for H.264 advanced video coding

Timing-driven placement based on monotone cell ordering constraints

Area optimization for leakage reduction and thermal stability in nanometer scale technologies

Fast multi-domain clock skew scheduling for peak current reduction

Jitter decomposition in ring oscillators

Closed form solution for optimal buffer sizing using the Weierstrass elliptic function

Delay variation tolerance for domino circuits

An automated design flow for 3D microarchitecture evaluation

Optimization of circuit trajectories: an auxiliary network approach

EDA vendor adoption

Hardware debugging method based on signal transitions and transactions

POSIX modeling in SystemC

Interconnect RL extraction at a single representative frequency

A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation

Delay modeling and static timing analysis for MTCMOS circuits

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

Parasitics extraction involving 3-D conductors based on multi-layered Green's function

Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)

Hardware architecture design of an H.264/AVC video codec

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers

Maximizing data reuse for minimizing memory space requirements and execution cycles

Power distribution techniques for dual VDD circuits

A cycle accurate power estimation tool

Abridged addressing: a low power memory addressing strategy

Cache size selection for performance, energy and reliability of time-constrained systems

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Refinement strategies for verification methods based on datapath abstraction

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Crosstalk analysis using reconvergence correlation

Ultra-low voltage power management circuit and computation methodology for energy harvesting applications

Mapping and configuration methods for multi-use-case networks on chips

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Constraint driven I/O planning and placement for chip-package co-design

Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology

Low area pipelined circuits by multi-clock cycle paths and clock scheduling

A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels

An O(mn) time algorithm for optimal buffer insertion of nets with m sinks

Efficient identification of multi-cycle false path

Optimal topology exploration for application-specific 3D architectures

SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices

Utility of the OpenAccess database in academic research

Cycle error correction in asynchronous clock modeling for cycle-based simulation

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

An efficient algorithm for 3-D reluctance extraction considering high frequency effect

PowerViP: Soc power estimation framework at transaction level

Switching-activity driven gate sizing and Vth assignment for low power design

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications

A novel framework for multilevel full-chip gridless routing

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

Signal-path driven partition and placement for analog circuit

A probabilistic analysis of pipelined global interconnect under process variations

ASIP approach for implementation of H.264/AVC

Design space exploration for minimizing multi-project wafer production cost

Compiler-Guided data compression for reducing memory consumption of embedded applications

Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

Using speculative computation and parallelizing techniques to improve scheduling of control based designs

Reducing dynamic compilation overhead by overlapping compilation and execution

Statistical Bellman-Ford algorithm with an application to retiming

Generation of shorter sequences for high resolution error diagnosis using sequential SAT

Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization

Process-induced skew reduction in nominal zero-skew clock trees

A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression

Conversion of reference C code to dataflow model: H.264 encoder case study

Prefetching-aware cache line turnoff for saving leakage energy

Simultaneous block and I/O buffer floorplanning for flip-chip design

A transduction-based framework to synthesize RSFQ circuits

Double edge triggered Feedback Flip-Flop in sub 100NM technology

Spec-based flip-flop and latch repeater planning

IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults

Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems

An unconditional stable general operator splitting method for transistor level transient analysis

A fast logic simulator using a look up table cascade emulator

Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs

Macromodelling oscillators using Krylov-subspace methods

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs

A novel instruction scratchpad memory optimization method based on concomitance metric

Monotonic parallel and orthogonal routing for single-layer ball grid array packages

A memory grouping method for sharing memory BIST logic

An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis

Yield-preferred via insertion based on novel geotopological technology

SAT-based optimal hypergraph partitioning with replication

Analysis of scratch-pad and data-cache performance using statistical methods

Controlling inductive cross-talk and power in off-chip buses using CODECs

Worst case execution time analysis for synthesized hardware

Functional modeling techniques for efficient SW code generation of video codec applications

An exact algorithm for the statistical shortest path problem

An implementation of a CMOS down-conversion mixer for GSM1900 receiver

Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors

Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback

A built-in power supply noise probe for digital LSIs

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices

High-throughput decoder for low-density parity-check code

Hardware implementation of super minimum all digital FM demodulator

Designing a custom architecture for DCT using NISC technology

A 52mW 1200MIPS compact DSP for multi-core media SoC

Implementation of H.264/AVC decoder for mobile video applications

A high-performance platform-based SoC for information security

Configurable multi-processor architecture and its processor element design

Design and implementation of transducer for ARM-TMS communication

Proceedings of the 2006 Asia and South Pacific Design Automation Conference (ASP-DAC '06)

Content Provider	ACM Digital Library
Editor	Hirose, Fumiyasu Tago, Haruyuki Pan, David Z. Hamaguchi, Kiyoharu Yamashita, Shigeru Parameswaran, Sri Sylvester, Dennis Minato, Shin'ichi Shiraishi, Youichi Chen, Charlie Chung-Ping Ohtake, Satoshi Gauthier, Lovic Khatri, Sunil Fujimoto, Ryuichi Shin, Youngsoo Sapatnekar, Sachin Chang, Yao-Wen Takeuchi, Yoshinori Asai, Hideki Min, Sang Lyul Ekpanyapong, Mongkol Jerraya, Ahmed Darringer, John Arakawa, Takahiko Lin, Youn-Long Huang, Juinn-Dar Hashizume, Masaki Zhu, Qiang Sato, Takashi Sakallah, Karem Chang, Shih-Chieh Pitchumani, Vijay Masuda, Hiroo Hatayama, Kazumi Wakabayashi, Shin'ichi Menezes, Noel Wang, Ting-Chi Jing, Tong Shi, C. J. Richard Roychowdhury, Jaijeet Nagata, Makoto Tan, Sheldon Moriyama, Seijiro Kajihara, Seiji Bertacco, Valeria Kimura, Shinji Kimura, Tomohisa Yamaguchi, Ryuichi Wolf, Wayne Panda, Preeti Ranjan Tomiyama, Hiroyuki Park, In-Cheol Ismail, Yehea Kobayashi, Kazutoshi Amano, Hideharu Nakatake, Shigetoshi Ha, Soonhoi Ikeda, Makoto Ishihara, Tohru Kurokawa, Atsushi Young, Evangeline F. Y. Matsushita, Satoshi
Copyright Year	2006
Abstract	On behalf of the Organizing Committee, I would like to welcome you to the Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006) being held here at Pacifico Yokohama jointly with the Electronic Design and Solution Fair 2006. ASP-DAC is a sister conference of DAC, DATE and ICCAD, and it is the 11th event of this conference series.ASP-DAC is the meeting place where researchers and engineers come together to learn and discuss state of the art technologies of system/SoC design, EDA and design methodologies. This year, we put special effort into attracting designers and design industries to produce Designers' Forum.We have three keynote speakers from academia, the semiconductor industry and the systems industry. Professor Alberto Sangiovanni-Vincentelli, University of California at Berkeley, will explore future system design perspectives in automotive electronics. Satoru Ito, President & CEO of RENESAS Technology Corp. will discuss challenges of device innovation. Yukichi Niwa, Senior Advisory Director of CANON INC. will present the company's key concept of architecting platform based design.The technical program was selected from 424 papers from 27 countries. The 64 members of the Technical Program Committee chaired by Professor Onodera and helped by over 250 reviewers had to make difficult choices to carefully select 135 papers. It is an outstanding program that covers a variety of key topics from system level design to physical design. Designers' Forum is a new program that shares design experience and solutions of real product designs of the industries whose topics include the CELL and mobile designs, panels of top 10 design issues and system verification. The University Design Contest is also an important event of ASP-DAC, which focuses on a real chip design in academia. On Tuesday, one full-day and six half-day tutorials are scheduled to provide introductions to hot topics like DFM, lowpower, packaging/interconnect, system level design and verification.
Related Links	http://www.aspdac.com
ISBN	0780394518
Language	English
Publisher	IEEE Press
Publisher Date	2006-01-24
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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