NDLI: A novel instruction scratchpad memory optimization method based on concomitance metric

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A novel instruction scratchpad memory optimization method based on concomitance metric

Content Provider	ACM Digital Library
Author	Ignjatović, Aleksandar Janapsatya, Andhi Parameswaran, Sri
Abstract	Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated that scratchpad memory can significantly reduce the energy consumption of the memory hierarchy of embedded systems. This is significant, as the memory hierarchy consumes a substantial proportion of the total energy of an embedded system. This paper deals with optimization of the instruction memory scratchpad based on a novel methodology that uses a metric which we call the concomitance. This metric is used to find basic blocks which are executed frequently and in close proximity in time. Once such blocks are found, they are copied into the scratchpad memory at appropriate times; this is achieved using a special instruction inserted into the code at appropriate places. For a set of benchmarks taken from Mediabench, our scratchpad system consumed just 59% (avg) of the energy of the cache system, and 73% (avg) of the energy of the state of the art scratchpad system, while improving the overall performance. Compared to the state of the art method, the number of instructions copied into the scratchpad memory from the main memory is reduced by 88%.
Starting Page	612
Ending Page	617
Page Count	6
File Format	PDF
ISBN	0780394518
DOI	10.1145/1118299.1118443
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-01-24
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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