NDLI: Low power design techniques for nanometer design processes: 65 nm and smaller

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Low power design techniques for nanometer design processes: 65 nm and smaller

Content Provider	ACM Digital Library
Author	Chattopadhyay, Subhomoy
Abstract	Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs in the 65nm and smaller geometries. The amount of logic that goes on a SOC is determined by the power envelope of the part for the applications that the part would support. In this tutorial I am presenting the importance of low power design techniques and methodologies for microprocessor/SOC design from the high level micro architectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers in the 65nm and smaller geometries. Embedded microprocessor/SOC designs are particularly dictated by standby and max/thermal design power and battery life constraints. Performance/watt or MIPS/watt is the design metric of today that we focus on in the sub 65nm geometries. We cover the main components of leakage power and elaborate on the transistor design characteristics for low power. A short discussion of different process variants for various types of applications will also be discussed followed by an introduction of shadow latches and state retention techniques used by microprocessors and DSPs of today. Tradeoff between amount of state retained and the exit latency of the processor from deep sleep/standby states will be discussed. In short this tutorial attempts to provide a broad overview on the importance of low power design methodologies for SOC/ASICs in the sub 65nm era. It also discusses the state of the art techniques for lower power design for wireless and mobile applications.
Starting Page	5
Ending Page	5
Page Count	1
File Format	PDF
ISBN	9781595938169
DOI	10.1145/1284480.1284486
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-09-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	65 nm Embedded design Low power
Content Type	Text
Resource Type	Article

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