NDLI: Aquarius: a dynamically reconfigurable computing platform

Please wait, while we are loading the content...

Highly sensitive, low-cost integrated biosensors

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

A ultra low power CMOS pA/V transconductor and its application to wavelet filters

Current mode instrumentation amplifier with rail-to-rail input and output

On the design of ultra low noise amplifiers for ENG recording

Model driven engineering for MPSOC design space exploration

Buffer sizing for QoS flows in wormhole packet switching NoCs

A 9.6 kb/s CMOS FSK modem for data transmission through power lines

A CMOS AM demodulator for instrumentation applications

A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA

A reconfigurable platform for multi-service edge routers

Bus encoding schemes for minimizing delay in VLSI interconnects

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach

High-speed, model-free adaptive control using parallel synchronous detection

Contributions to improve design accuracy of bipolar ics via physical effects

Layout techniques for radiation hardening of standard CMOS active pixel sensors

Minimizing the mismatch errors at the VCO and cascode buffer connections in front end of BiCMOS RFICs operating on S band.

A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs

Parallelized radix-4 scalable montgomery multipliers

Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models

An optimized hybrid approach to provide fault detection and correction in SoCs

Meeting with the forthcoming IC design

Suppression of delta-sigma DAC quantisation noise by bandwidth adaptation

A programmable voltage reference optimized for power management applications

A multisampling time-domain CMOS imager with synchronous readout circuit

Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications

Cell placement on graphics processing units

Fitting the router characteristics in NoCs to meet QoS requirements

A 4.1 GHz prescaler using double data throughput E-TSPC structures

Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop

Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture

Aquarius: a dynamically reconfigurable computing platform

A built-in current sensor for high speed soft errors detection robust to process and temperature variations

Instantaneous de-embedding of the on-wafer equivalent-circuit parameters of acoustic resonator (FBAR) for integrated circuit applications

Radial basis function network applied to the linearization of a voltage controlled oscillator

A quasi-differential quantizer based on SMOBILE

Total ionizing dose effects in switched-capacitor filters using oscillation-based test

A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface

Cache coherency communication cost in a NoC-based MPSoC platform

A time petri net-based approach for hard real-time systems scheduling considering dynamic voltage scaling, overheads, precedence and exclusion relations

FPGA infrastructure for the development of augmented reality applications

A software-based methodology for the generation of peripheral test sets based on high-level descriptions

WiMAX: a competing or complementary technology to 3G?

Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS

Trim range limited by noise in bandgap voltage references

A systematic method to approximate capacitance ratios to improve capacitance matching in SC filters

Design of a class D amplifier for hearing aid devices

A comparative study of CMOS gates with minimum transistor stacks

Router architecture for high-performance NoCs

TrACS: transceiver architecture and wireless channel simulator

Digital PM demodulator for brazilian data collecting system

RoSA: a reconfigurable stream-based architecture

Design of adaptive multiprocessor on chip systems

Soft-well digital circuit design

Three-dimensional on-chip inductance and resistance extraction

Viability of analog inner product operations in CMOS imagers

A 915 MHz UHF low power RFID tag

The interval page table: virtual memory support in real-time and memory-constrained embedded systems

Object and method exploration for embedded systems applications

Using majority logic to cope with long duration transient faults

Nanotechnology and emerging memories

High-speed CMOS analog-to-digital converter for front-end receiver applications

Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs)

CMOS encoder for scale-independent pattern recognition

A soft error robust and power aware memory design

Analysis of the use of declarative languages for enhanced embedded system software development

Functional verification of an MPEG-4 decoder design using a random constrained movie generator

Low power design techniques for nanometer design processes: 65 nm and smaller

RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities

First-pass-silicon radio IPs for B3G wireless networks

Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems

Embedded non-volatile memories

Aquarius: a dynamically reconfigurable computing platform

Content Provider	ACM Digital Library
Author	Barbosa, Edson Nascimento, Paulo Sergio B. Eskinazi, Remy Seixas, Jordana Silva, Stelita Eusebio, Manoel Barros, Edna Kursancew, Vinícius
Abstract	This work presents the development of a dynamically reconfigurable computing platform targeting Virtex-II devices under control of a host system based on the Nios II soft-core processor from Altera. The platform, called Aquarius, controls the system by means of the μCLinux embedded Operating System (OS). Through this OS, an IP-SelectMAP core and its device driver, a Virtex-II FPGA device can be totally or partially reconfigured. Given that the partial reconfiguration does not affect the other running areas the partial reconfiguration is dynamic. Two programs have been developed in order to validate both reconfiguration styles. This programs control the application tasks execution and their respective bitstreams, according to the task's scheduling. The platform has been prototyped and an example has been developed and is presented in this work.
Starting Page	171
Ending Page	176
Page Count	6
File Format	PDF
ISBN	9781595938169
DOI	10.1145/1284480.1284530
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-09-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpgas Tasks scheduling Bitstream Dynamic reconfiguration Prototyping Μclinux Device driver
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in