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  1. Proceedings of the 11th International Workshop on Data Management on New Hardware (DaMoN'15)
  2. Applying HTM to an OLTP System: No Free Lunch
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Energy-Efficient In-Memory Data Stores on Hybrid Memory Hierarchies
Beyond the Wall: Near-Data Processing for Databases
Scaling the Memory Power Wall With DRAM-Aware Data Management
NUMA obliviousness through memory mapping
By their fruits shall ye know them: A Data Analyst's Perspective on Massively Parallel System Design
TLB misses: The Missing Issue of Adaptive Radix Tree?
Applying HTM to an OLTP System: No Free Lunch
The Serial Safety Net: Efficient Concurrency Control on Modern Hardware
Efficient Lightweight Compression Alongside Fast Scans
Energy-Efficient Query Processing on Embedded CPU-GPU Architectures
Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries
Ultra-Fast Similarity Search Using Ternary Content Addressable Memory

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Applying HTM to an OLTP System: No Free Lunch

Content Provider ACM Digital Library
Author Porobic, Danica Cervini, David Tözün, Pınar Ailamaki, Anastasia
Abstract Transactional memory is a promising way for implementing efficient synchronization mechanisms for multicore processors. Intel's introduction of hardware transactional memory (HTM) into their Haswell line of processors marks an important step toward mainstream availability of transactional memory. Transaction processing systems require execution of dozens of critical sections to insure isolation among threads, which makes them one of the target applications for exploiting HTM. In this study, we quantify the opportunities and limitations of directly applying HTM to an existing OLTP system that uses fine-grained synchronization. Our target is Shore-MT, a modern multithreaded transactional storage manager that uses a variety of fine-grained synchronization mechanisms to provide scalability on multicore processors. We find that HTM can improve performance of the TATP workload by 13--17% when applied judiciously. However, attempting to replace all synchronization reduces performance compared to the baseline case due to high percentage of aborts caused by the limitations of the current HTM implementation.
Starting Page 1
Ending Page 7
Page Count 7
File Format PDF
ISBN 9781450336383
DOI 10.1145/2771937.2771946
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2015-05-31
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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