NDLI: Architecture of the PSC-a programmable systolic chip

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Architecture of the PSC-a programmable systolic chip

Content Provider	ACM Digital Library
Author	Fisher, Allan L. Monier, Louis M. Kung, H. T. Dohi, Yasunori
Abstract	In recent years, many systolic algorithms have been proposed as solutions to computationally demanding problems in signal and image processing and other areas. Such algorithms exploit the regularity and parallelism of problems to achieve high performance and low I/O requirements. Since systolic algorithms generally consist of a few types of simple processors, or systolic cells, connected in a regular pattern, they are less expensive to design and implement than more general machines. This advantage is offset by the fact that a particular systolic system can generally be used only on a narrow set of problems, and thus design cost cannot be amortized over a large number of units. One way to approach this problem is to provide a programmable systolic chip (PSC), many copies of which can be connected and programmed to implement many systolic algorithms. The systolic environment, by virtue of its emphasis on continuous, regular flow of data and fairly simple per-cell processing, imposes new design requirements for programmable processors which are quite different from those found in a general-purpose system. This paper describes the CMU PSC, a single-chip microprocessor suitable for use in groups of tens or hundreds for the efficient implementation of a broad variety of systolic arrays. The processor has been fabricated in nMOS, and is undergoing testing.
Starting Page	48
Ending Page	53
Page Count	6
File Format	PDF
ISBN	0897911016
DOI	10.1145/800046.801637
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-06-13
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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