NDLI: Trading defect tolerance for chip area in nanotecnology implementations of systolic arrays

Content Provider	IEEE Xplore Digital Library
Author	Ciric, V. Simic, V. Cvetkovic, A. Milentijevic, I.
Copyright Year	2012
Description	Author affiliation: Faculty of Electronic Engineering, University of Niš, Serbia (Ciric, V.; Simic, V.; Milentijevic, I.) \|\| Faculty of Mechanical Engineering, University of Belgrade, Serbia (Cvetkovic, A.)
Abstract	New self-assembling techniques used to build nano-scale architecture prototypes have a drawback of being prone to defects and transient faults. Fault and defect tolerance techniques will be crucial to the use of nano-electronics in the future. However, these techniques usually introduce a significant hardware overhead. In these paper we are proposing a method for trading an architecture tolerance on fabrication defects for chip area. The method will be presented using an architecture with generic topology and illustrated on the example of partially defect tolerant bit-plane semi-systolic array. In order to illustrate the method the results of FPGA implementation of completely fault tolerant bit-plane array, and partially fault tolerant bit-plane array will be given.
Starting Page	1083
Ending Page	1086
File Size	474789
Page Count	4
File Format	PDF
ISBN	9781467307826
ISSN	21588473
e-ISBN	9781467307840
DOI	10.1109/MELCON.2012.6196616
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-25
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Fault tolerant systems Field programmable gate arrays Architecture Hardware Redundancy
Content Type	Text
Resource Type	Article

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