NDLI: Stealth prefetching

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A comparison of software and hardware techniques for x86 virtualization

AVIO: detecting atomicity violations via access interleaving invariants

Ultra low-cost defect protection for microprocessor pipelines

Mercury and freon: temperature emulation and management for server systems

A spatial path scheduling algorithm for EDGE architectures

A performance counter architecture for computing accurate CPI components

Comprehensively and efficiently protecting the heap

A defect tolerant self-organizing nanoscale SIMD architecture

Stealth prefetching

Mapping esterel onto a multi-threaded embedded processor

Hybrid transactional memory

A new idiom recognition framework for exploiting hardware-assist instructions

Impact of virtualization on computer architecture and operating systems

Geiger: monitoring the buffer cache in a virtual machine environment

A regulated transitive reduction (RTR) for longer memory race recording

Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance

PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor

Instruction scheduling for a tiled dataflow architecture

Accurate and efficient regression modeling for microarchitectural performance and power prediction

HeapMD: identifying heap-based bugs using anomaly detection

A program transformation and architecture support for quantum uncomputation

Computation spreading: employing hardware migration to specialize CMP cores on-the-fly

Integrated network interfaces for high-bandwidth TCP/IP

Unbounded page-based transactional memory

Automatic generation of peephole superoptimizers

Temporal search: detecting hidden malware timebombs with virtual machines

Bell: bit-encoding online memory leak detection

SlicK: slice-based locality exploitation for efficient redundant multithreading

Exploiting coarse-grained task, data, and pipeline parallelism in stream programs

Efficiently exploring architectural design spaces via predictive modeling

Recording shared memory dependencies using strata

Introspective 3D chips

Software-based instruction caching for embedded processors

Accelerator: using data parallelism to program GPUs for general-purpose uses

Supporting nested transactional memory in logTM

Combinatorial sketching for finite programs

Tartan: evaluating spatial computation for whole program execution

Tradeoffs in transactional memory virtualization

A probabilistic pointer analysis for speculative optimizations

Stealth prefetching

Content Provider	ACM Digital Library
Author	Lipasti, Mikko H. Smith, James E. Cantin, Jason F.
Abstract	Prefetching in shared-memory multiprocessor systems is an increasingly difficult problem. As system designs grow to incorporate larger numbers of faster processors, memory latency and interconnect traffic increase. While aggressive prefetching techniques can mitigate the increasing memory latency, they can harm performance by wasting precious interconnect bandwidth and prematurely accessing shared data, causing state downgrades at remote nodes that force later upgrades.This paper investigates Stealth Prefetching, a new technique that utilizes information from Coarse-Grain Coherence Tracking (CGCT) for prefetching data aggressively, stealthily, and efficiently in a broadcast-based shared-memory multiprocessor system. Stealth Prefetching utilizes CGCT to identify regions of memory that are not shared by other processors, aggressively fetches these lines from DRAM in open-page mode, and moves them close to the processor in anticipation of future references. Our analysis with commercial, scientific, and multiprogrammed workloads show that Stealth Prefetching provides an average speedup of 20% over an aggressive baseline system with conventional prefetching.
Starting Page	274
Ending Page	282
Page Count	9
File Format	PDF
ISBN	1595934510
DOI	10.1145/1168857.1168892
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-10-23
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multiprocessors Prefetching Coherence
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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Similar Documents

Stealth prefetching (CARN, Vol. 34, Issue. 5)

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