NDLI: Field programmable port extender (FPX) for distributed routing and queuing

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The effect of LUT and cluster size on deep-submicron FPGA performance and density

Programmable memory blocks supporting content-addressable memory

A novel high throughput reconfigurable FPGA architecture

An FPGA implementation and performance evaluation of the Serpent block cipher

Factoring large numbers with programmable hardware

Technology mapping for k/m-macrocell based FPGAs

Technology mapping issues for an FPGA with lookup tables and PLA-like blocks

Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays

Synthesis for FPGAs with embedded memory blocks

A reconfigurable multi-function computing cache architecture

A C compiler for a processor with a reconfigurable functional unit

The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers

A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms

The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips

A benchmark suite for evaluating configurable computing systems—status, reflections, and future directions

Field programmable port extender (FPX) for distributed routing and queuing

Implementing a RAKE receiver for wireless communications on an FPGA-based computer system

Generating highly-routable sparse crossbars for PLDs

New parallelization and convergence results for NC: a negotiation-based FPGA router

Automatic generation of FPGA routing architectures from high-level descriptions

Tolerating operational faults in cluster-based FPGAs

Power estimation approach for SRAM-based FPGAs

Timing-driven placement for FPGAs

Algorithm analysis and mapping environment for adaptive computing systems (poster abstract)

Coarse-grained carry architecture for FPGA (poster abstract)

Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract)

An FPGA-based genetic algorithm machine (poster abstract)

Design and implementation of an FPGA based processor for compressed images (poster abstract)

Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract)

Improving the performance and efficiency of an adaptive amplification operation using configurable hardware (poster abstract)

FPGA implementation and analysis of image restoration

FPGA clock management for low power applications (poster abstract)

Novel hardware-software architecture for the recursive merge filtering algorithm (poster abstract)

Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

Reconfigurable target recognition system (poster abstract)

Real-time, frame-rate face detection on a configurable hardware system (poster abstract)

Scalable interconnect and power distribution for island-style FPGAs (poster abstract)

Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract)

Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract)

Virtualization of FPGA via segmentation (poster abstract)

Field programmable port extender (FPX) for distributed routing and queuing

Content Provider	ACM Digital Library
Author	Turner, Jon S. Taylor, David E. Lockwood, John W.
Abstract	Field Programmable Gate Arrays (FPGAs) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the Field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic.FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports.Logic on the FPX module is implemented with two FPGA devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second FPGA can be reprogrammed dynamically via control cells sent over the network.The flexibility of the FPX has made the card of interest for several networking applications. This year, fifty FPX hardware modules will be fabricated and distributed to researchers at eight universities around the country who are interested in experimenting with reprogrammable networks and per-flow queuing mechanisms. The FPX hardware will first be used to implement fast IP lookup algorithms and distributed input queueing.
Starting Page	137
Ending Page	144
Page Count	8
File Format	PDF
ISBN	1581131933
DOI	10.1145/329166.329196
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2000-02-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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