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Content Provider | ACM Digital Library |
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Author | Mishra, Asit K. Kademir, Mahmut Chidambaram Nachiappan, Nachiappan Sivasubramaniam, Anand Das, Chita R. Mutlu, Onur |
Abstract | Data prefetching is an effective technique for hiding memory latency. When issued prefetches are inaccurate, performance can degrade. Prior research provided solutions to deal with inaccurate prefetches at the cache and memory levels, but not in the interconnect of a large-scale multiprocessor system. This work introduces application-aware prefetch prioritization techniques to mitigate the negative effects of prefetching in a network-on-chip (NoC) based multicore system. The idea is to rank prefetches from different applications based on their potential utility for the application and propensity to cause interference to other applications. Our evaluation shows that this approach provides significant performance improvements over a baseline that does not distinguish between prefetches from different applications. |
Starting Page | 441 |
Ending Page | 442 |
Page Count | 2 |
File Format | |
ISBN | 9781450311823 |
DOI | 10.1145/2370816.2370886 |
Language | English |
Publisher | Association for Computing Machinery (ACM) |
Publisher Date | 2012-09-19 |
Publisher Place | New York |
Access Restriction | Subscribed |
Subject Keyword | Interconnect Multicore Prefetching |
Content Type | Text |
Resource Type | Article |
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