NDLI: XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems

Please wait, while we are loading the content...

The changing role of supercomputing

Power-aware multi-core simulation for early design stage hardware/software co-optimization

Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme

PEPON: performance-aware hierarchical power budgeting for NoC based multicores

Pointy: a hybrid pointer prefetcher for managed runtime systems

Evaluation of Blue Gene/Q hardware support for transactional memories

Compiling to avoid communication

Visualizing transactional memory

RISE: improving the streaming processors reliability against soft errors in gpgpus

Top500 versus sustained performance: the top problems with the top500 list - and what to do about them

Practically private: enabling high performance CMPs through compiler-assisted data classification

Runtime detection and optimization of collective communication patterns

Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches

Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads

The evicted-address filter: a unified mechanism to address both cache pollution and thrashing

Hardware acceleration in the IBM PowerEN processor: architecture and performance

LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures

Mileage-based contention management in transactional memory

PGCapping: exploiting power gating for power capping and core lifetime balancing in CMPs

Riposte: a trace-driven compiler and parallel VM for vector code in R

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems

Scalability-based manycore partitioning

Making data prefetch smarter: adaptive prefetching on POWER7

Sandboxing transactional memory

Chrysalis analysis: incorporating synchronization arcs in dataflow-analysis-based parallel monitoring

Complexity-effective multicore coherence

Coalition threading: combining traditional andnon-traditional parallelism to maximize scalability

Efficient techniques for predicting cache sharing and throughput

Multi2Sim: a simulation framework for CPU-GPU computing

A software memory partition approach for eliminating bank-level interference in multicore systems

Workload and power budget partitioning for single-chip heterogeneous processors

Acceleration of bulk memory operations in a heterogeneous multicore architecture

System-level power-performance efficiency modeling for emergent GPU architectures

Power-efficient time-sensitive mapping in heterogeneous systems

Auto-parallelizing stateful distributed streaming applications

APCR: an adaptive physical channel regulator for on-chip interconnects

Optimizing datacenter power with memory system levers for guaranteed quality-of-service

Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics

Transactional prefetching: narrowing the window of contention in hardware transactional memory

Probabilistic diagnosis of performance faults in large-scale parallel applications

HaLock: hardware-assisted lock contention detection in multithreaded applications

Shared memory multiplexing: a novel way to improve GPGPU throughput

Optimal bypass monitor for high performance last-level caches

A yoke of oxen and a thousand chickens for heavy lifting graph processing

Base-delta-immediate compression: practical data compression for on-chip caches

Database analytics acceleration using FPGAs

Integrating nanophotonics in GPU microarchitecture

Transactional event profiling in a best-effort hardware transactional memory system

Branch and data herding: reducing control and memory divergence for error-tolerant GPU applications

Transparent runtime deadlock elimination

Layout-oblivious optimization for matrix computations

Design of a storage processing unit

Boost.SIMD: generic programming for portable SIMDization

SkipCache: miss-rate aware cache management

Speculative parallelization needs rigor: probabilistic analysis for optimal speculation of finite-state machine applications

Using combined profiling to decide when thread level speculation is profitable

Supporting stateful tasks in a dataflow graph

Hardware prefetchers for emerging parallel applications

MaSiF: machine learning guided auto-tuning of parallel skeletons

Strategies based on green policies to the grid resource allocation

TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency

Linearly compressed pages: a main memory compression framework with low complexity and low latency

Application-aware prefetch prioritization in on-chip networks

Energy-efficient workload mapping in heterogeneous systems with multiple types of resources

ReCaP: a region-based cure for the common cold cache

Phase-based scheduling and thread migration for heterogeneous multicore processors

Power-efficient computing for compute-intensive GPGPU applications

Off-chip access localization for NoC-based multicores

Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing

PS-Dir: a scalable two-level directory cache

Inference and declaration of independence: impact on deterministic task parallelism

Application-to-core mapping policies to reduce memory interference in multi-core systems

Bandwidth bandit: quantitative characterization of memory contention

Speculative dynamic vectorization for HW/SW co-designed processors

Fine-grained parallel traversals of irregular data structures

High-performance analysis of filtered semantic graphs

Energy-efficient cache partitioning for future CMPs

A low-overhead dynamic optimization framework for multicores

Making it practical and effective: fast and precise may-happen-in-parallel analysis

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems

Content Provider	ACM Digital Library
Author	Das, Reetuparna Mudge, Trevor Sewell, Korey Dreslinski, Ronald G. Blaauw, David Satpathy, Sudhir Manville, Thomas Sylvester, Dennis Pinckney, Nathaniel
Abstract	With multi-core processors now mainstream, the shift to many-core processors poses a new set of design challenges. In particular, the scalability of coherence protocols remains a significant challenge. While complex Network-on-Chip interconnect fabrics have been proposed and in some cases implemented, most of industry has slowly evolved existing coherence solutions to meet the needs of a growing number of cores. Industries' slow adoption of Network-on-Chip designs is in large part due to the significant effort needed to design and verify the system. However, simply scaling bus-based coherence is not straightforward either because of increased contention and latency on the bus for large core counts. This paper proposes a new architecture, XPoint, which does not need to modify existing bus-based snooping coherence protocols to scale to 64 core systems. XPoint employs interleaved cache structures with detailed floorplaning and system analysis to reduce contention at high core counts. Results show that the XPoint system achieves, on average, a 28x and 35x over a single core design on the Splash2 benchmarks for a 32 and 64 core system respectively (a 1.6x improvement over a 64 core conventional bus). XPoint is also evaluated as a 3D stacked system to reduce further bus latency. Results show a 29x and 45x speedup for 32 and 64 core systems respectively (a 2.1x improvement over a 64 core conventional bus and within 8% of the speedup of a 64 core system with an ideal interconnect). Measurements also show that the XPoint system decreases bus contention of a 64 core system to only 13% higher than that of an 8-core design (a 29x improvement over a 64 core conventional bus).
Starting Page	75
Ending Page	86
Page Count	12
File Format	PDF
ISBN	9781450311823
DOI	10.1145/2370816.2370829
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-09-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Bus design Cache coherence Interconnect 3d integration
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in