NDLI: Proceedings of the 2004 international workshop on System level interconnect prediction (SLIP '04)

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Early and accurate analysis of SoCs: oxymoron or real?

Self-consistent power/performance/reliability analysis for copper interconnects

Interconnect width selection for deep submicron designs using the table lookup method

Evolution as the blind engineer: wiring minimization in the brain (Abstract only)

Optical solutions for system-level interconnect

Prediction of interconnect adjacency distribution: derivation, validation, and applications

Interconnect-power dissipation in a microprocessor

Investigation of performance metrics for interconnect stack architectures

A low power approach to system level pipelined interconnect design

A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)

Defect tolerance for nanocomputer architecture

Prediction of interconnect net-degree distribution based on Rent's rule

Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling

Topology optimization for application-specific networks-on-chip

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods

A statistical model for estimating the effect of process variations on crosstalk noise

Proceedings of the 2004 international workshop on System level interconnect prediction (SLIP '04)

Content Provider	ACM Digital Library
Editor	Scheffer, Lou Dambre, J. Sylvester, D. Scheffer, L. Hutton, M. Markov, Igor Bennebroek, M. Stroobandt, D.
Copyright Year	2004
Abstract	On behalf of the organizing committee, we would like to welcome you to the 2004 International Workshop on System Level Interconnect Prediction (SLIP 2004).Interconnect modelling and analysis are not just important - they are becoming crucial to the design of all modern chips. Fabs and foundries are making difficult, risky, and expensive process changes (such as copper wires and low-k dielectrics) just to make interconnect work slightly better. Commercial tool vendors are now stressing the importance of interconnect planning and early implementation of wires, even in fully custom chips. Vendors of chips with fixed wiring capacity such as gate arrays and FPGAs have a direct and first order interest in interconnect prediction, since the interconnect must be built into the chip before the designs are known. Excess capacity remains unused and hurts cost and performance, while insufficient capacity may prevent some designs from fitting into the device. If you are at all interested in IC design, your work will be in some way touched by the problems of interconnect prediction.Interconnect problems occur wherever chips are built or designed, so SLIP has always had participants from many countries. However, up until now, it has always been held in the USA in conjunction with ISPD, the International Symposium on Physical Design. This has always been on the west coast of the United States in early April. This year we are trying something new - we are holding the workshop in conjunction with DATE, the European Design and Test conference. Although this made the conference earlier, shortening the time for submissions, our hope was that this would encourage the participation of additional universities, researchers, and companies. This hope has been realized, with presentations from France, Belgium, Italy, Finland, and Singapore. Prof. Dirk Stroobandt of Ghent University was the driving force behind this change of venue, has made all the local arrangements, and has given particularly strong support for SLIP in general. We owe him many thanks for his tireless work in support of this conference. There is, however, no truth to the rumor that he is changing his name to 'Rent'.This year we have papers in the traditional areas of statistical modelling, the effects of technology migration, and application specific interconnect schemes. We also have an invited paper in a field that has up until now been completely unrelated - the wiring of the brain. Although the brain was designed by very different methods than we use for chips, and is made of different materials with different constraints, the same general problems of local and distant communication must occur. Nature has had much longer to build optimized solutions, but it's much easier to study the wiring in a chip, so perhaps each group can learn from the other.SLIP 2004 is sponsored by ACM/SIGDA and the IEEE, and the proceedings are published by the ACM. The talks are a mixture of contributed papers, invited presentations, and tutorials. As usual, contributers are invited to submit their work for consideration for a special issue of TVLSI devoted to the problems of interconnect prediction and planning.
ISBN	1581138180
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-02-14
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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