NDLI: Interconnect-power dissipation in a microprocessor

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Interconnect-power dissipation in a microprocessor

Content Provider	ACM Digital Library
Author	Kolodny, Avinoam Weiser, Uri Shamir, Nachum Magen, Nir
Abstract	Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50% of the dynamic power. Over 90% of the interconnect power is consumed by only 10% of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router's algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14% in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.
Starting Page	7
Ending Page	13
Page Count	7
File Format	PDF
ISBN	1581138180
DOI	10.1145/966747.966750
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-02-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Interconnect power Routing Low-power design Wire spacing
Content Type	Text
Resource Type	Article

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