NDLI: MP/C: A multiprocessor/computer architecture

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MP/C: A multiprocessor/computer architecture

Content Provider	ACM Digital Library
Author	Arden, Bruce W. Ginosar, Ran
Abstract	A computer architecture for concurrent computing is proposed that has the shared memory aspect of tightly coupled multiprocessor systems and also the connection simplicity associated with message-connected, loosely coupled multicomputer systems. A large address space is dynamically partitioned into contiguous segments that can be accessed by a single processor. The partitioning is accomplished by switching the system buses, using semiconductor switches. The completion of a concurrent process is signaled by a processor's return to an idle state and the reattachment of its memory segment to the neighboring active processor. In effect, the assignment of an address sequence and the activation of a processor is a process FORK operation, and the processor deactivation and memory segment reattachment is a process JOIN. Following a description of the MP/C structure and basic operation, some additional enhancements of the system, which improve the applicability of MP/C to many classes of computations, are outlined. Applications include tree-structured multiprocessing, recursive and nondeterministic procedures, arbitrary concurrent computations, very high precision numeric calculations, and process-structured operating systems. The linear MP/C structure is extensible to higher dimensions. A two-dimensional system is described, and its usefulness for data base operations and array processing is discussed.
Starting Page	3
Ending Page	19
Page Count	17
File Format	PDF
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-05-12
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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