NDLI: Proceedings of the conference on European design automation (EURO-DAC '90)

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Generation of embedded RAMs with built-in test using object-oriented programming

A database interface for phased tool integration

On the notion of the normal form register-level structures and its applications in design-space exploration

Synthesis of delay functions in DSP compilers

NETHDL: abstraction of schematics to high-level HDL

An algebraic model for design space with applications to function module generation

A neural net based self organising scheduling algorithm

Silicon compilation of switched: capacitor networks

Optimal via-shifting in channel compaction

An iterative algorithm for the binate covering problem

An event-driven transient simulation algorithm for MOS and bipolar circuits

CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP

Open-ended system for high-level synthesis of flexible signal processors

The EVE companion simulator

An efficient placement method for large standard-cell and sea-of-gates designs

On the fault coverage of delay fault detecting tests

A data-structuring technique for gridded VLSI layouts

Hierarchical layout verification for submicron designs

A new switch-level test pattern generation algorithm based on single path over a graph representation

Economics of point accelleration

MOLE: a sea-of-gates detailed router

Diagnosis oriented test pattern generation

SPI: an open interface integrating highly interactive electronic CAD tools

Formal verification of timing conditions

Efficent suboptimal state assignment for large sequential machines

Transmission gate delay models for circuit optimization

Solution of a module orientation and rotation problem

An architecture for synthesis of testable finite state machines

The effectiveness of different test sets for PLAs

Pre-placement of VLSI blocks through learning neural networks

ASTA: an integrated system for bist analysis & automatic test generation

On the architecture of a CAD framework: the NELSIS approach

Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level

A branch-and-bound method for optimal transformation of data flow graphs for observing hardware constraints

Comparison of implementations of real arithmetic in ELLA and VHDL

Transistor placement and interconnect algorithms for leaf cell synthesis

Interconnect optimisation during data path allocation

An intelligent design system for analogue integrated circuits

Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region

Technology mapping using boolean matching and don't care sets

PLATO: a new piecewise linear simulation tool

A VLSI floorplanner based on "balloon" expansion

System synthesis using behavioural descriptions

An incremental functional simulator implemented on a network of transputers

VLSI: placement based on routing and timing information

Some relationships between delay testing and stuck-open testing in CMOS circuits

An object-oriented persistent database interface for CAD

CIRCE: a program for parasitic parameter extraction

Fault modelling and fault equivalence in CMOS technology

Logic optimization on a concurrent processing computer

Channel routing with non-terminal doglegs

PROOFS: a super fast fault simulator for sequential circuits

A procedural interface to CAD data based on EDIF

SLOCOP-II: a versatile timing verification system for MOSVLSI

Multi-level synthesis on PALs

An accurate model for ambiguity delay simulation

A new algorithm for transistor sizing in CMOS circuits

CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler

Fully testable PLA design with minimal extra input

Fuzzy set based initial placement for IC layout

Tools and devices supporting the pseudo-exhaustive test

Design data management in a distributed hardware environment

Formal boolean manipulations for the verification of sequential machines

SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system

MINT: a VHDL simulation system

A flexible hierarchical 3-D module assembler

Matching system and component behaviour in MIMOLA synthesis tools

A graphical system for hierarchical specifications and checkups of VLSI circuits

An efficient two-dimensional compaction algorithm for VLSI symbolic layout

Gate sizing in MOS digital circuits with linear programming

Event-driven behavioural simulation of analogue transfer functions

A system for floorplanning with hierarchical placement and wiring

Towards a global solution to high level synthesis problems

Derivation of signal flow for switch-level simulation

Optimal slicing of plane point placements

Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks

Design management within a design environment

An improved layout verification algorithm (LAVA)

A strategy for testability enhancement at layout level

The use of computer-aided software engineering technology in systems and software design

On the k-layer planar subset and via minimization problems

High level test generation using data flow descriptions

Ghost/Spook: user interface and process management in the PACE framework

Automatic generation of timing specifications for CMOS transistor subnetworks

State assignment of controllers for optimal area implementation

Switch-level timing models in the MOS simulator BRASIL

Cell based performance optimization of combinational circuits

Fuzzy specification of finite state machines

PEST: a tool for implementing pseudo-exhaustive self test

GASP: a Genetic Algorithm for Standard cell Placement

Development of test programs with the aid of a testeroriented pattern language

The NMP-CADLAB framework: a common framework for tool integration and development

Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment

A new approach to pipeline optimisation

Structured analysis and VHDL in embedded ASIC design and verification

PARAGON: a new package for gate matrix layout synthesis

Redesign using state splitting

Automatic knowledge acquisition in a digital circuit design system

CACTUS: a symbolic CMOS two-dimensional compactor

A new synthesis technique for multilevel combinational circuits

A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation

ACCORDO: second generation floor planning

Multirate integration in a direct simulation method

A gate-matrix oriented partitioning approach for multilevel logical networks

Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring

A design representation for high level synthesis

Simulation based verification of register-transfer level behavioral synthesis tools

Accelerated test pattern generation by cone-oriented circuit partitioning

Rapid prototyping using high density interconnects

Path search on rectangular floorplan

Experience in functional-level test generation and fault coverage in a silicon compiler

Storage mechanism for VHDL intermediate form

Path runner: an accurate and fast timing analyser

A new method for the state reduction of incompletely specified finite sequential machines

Software architecture of universal hardware modeler

A dynamic programming approach to the power supply net sizing problem

Design for verification testability

A new clustering approach and its application to BBL placement

Design to test migration: a tester and a simulator

NAUTILE: a safe environment for silicon compilation

Proceedings of the conference on European design automation (EURO-DAC '90)

Content Provider	ACM Digital Library
Editor	Adshead, Gordon Jess, Jochen
Copyright Year	1990
Abstract	On behalf of the EDAC 90 Organising and Technical Programme Committee, it is our pleasure to welcome the participants of the first European Conference on Design Automation, and to present to you this Digest of Technical Papers.We are particularly pleased that this new European venture has generated great excitement and interest world-wide and has gained full support from the IEEE Computer Society. The research programme of the European Community had undoubtedly a substantial part in the stimulation of this activity. Ever since Esprit was launched, the European workers in DA from both industry and university have begun to experience a feeling of achievement, strength, mutual respect and community throughout the 12 member countries and beyond. Following the highly successful series of CAVE workshops, the time is now ripe for a major European-based international forum and publications base for VLSI design technology. The EDAC association has been formed and will be consolidated at the conference to promote a series of high quality technical DA conferences across Europe. We have already booked Amsterdam for EDAC 91.The response to the call for papers was overwhelming. 303 papers were received from 31 countries world-wide with nearly 70 per cent from Europe in its widest sense. The technical Programme Committee of 45 included Japanese and US members and has done an excellent job in selecting the best papers to be presented. The average quality was very high and easily matched the highest international standards. The Programme Committee was divided into 6 topic areas and every member reviewed all papers in that subject. At the first programme review meeting in Schipol it was unanimously agreed to accept 120 verbal presentations organised into 3 parallel sessions and a number of poster presentations.In addition to the technical presentations, the Committee has organised a panel session, a number of fringe meetings and 'birds of a feather' sessions for special interest groups, a day of tutorials and some vendor presence. All lunches, two evening receptions and the conference banquet are included in the fee. Members of IEEE/DATC, ACM/SlGDA and all European professional societies are especially encouraged to attend.We feel that you can be assured of a highly worthwhile technical forum during your visit to Glasgow in March. Thank you for participating in EDAC 90.
ISBN	0818620242
Language	English
Publisher	IEEE Computer Society Press
Publisher Date	1990-03-12
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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