NDLI: Proceedings of the conference on European design automation (EURO-DAC '91)

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Fast functional evaluation of candidate OBDD variable orderings

Tool communication in an integrated synthesis environment

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

An approach to the analysis and test of crosstalk faults in digital VLSI circuits

Formal sizing rules of CMOS circuits

Address Generation for array access based on modulus m counters

Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator

Glue-logic partitioning for floorplans with a rectilinear datapath

Exact and heuristic algorithms for the minimization of incompletely specified state machines

Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment

An algorithm for improving optimal placement for river-routing

TATOO: an industrial timing analyzer with false path elimination and test pattern generation

Test scheduling and controller synthesis in the CADDY-system

Area and performance optimizations in path-based scheduling

Parallel switch-level simulation for VLSI

Floorplanning strategy for mixed analog-digital VLSI integrated circuits

Optimization of micro-controllers by partitioning

The VLSI-programming language tangram and its translation into handshake circuits

GENVIEW: a portable source-level debugger for macrocell generators

Improved force-directed scheduling

Switch and logic-level modeling in EDIF 200: limitations and proposed solutions

An automatic synthesizer for CMOS operational amplifiers

Symbolic implication in test generation

Circuit partitioning into small sets: a tool to support testing with further applications

Technology mapping for a two-output RAM-based field programmable gate array

Concurrent MIN-MAX simulation

A performance analysis tool for performance-driven micro-cell generation

Resolution-based correctness proofs of synchronous circuits

A distributed engineering database management system for IC design

PHIFACT a design space exploration program

Detection of PLA multiple crosspoint faults

Delay estimation for CMOS functional cells

High level synthesis: a data path partitioning method dedicated to speed enhancement

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits

Towards optimizing global MinCut partitioning

Fast heuristic algorithms for finite state machine minimization

HITEC: a test generation package for sequential circuits

An integrated layout system for sea-of-gates module generation

TAS: an accurate timing analyser for CMOS VLSI

Synthesis of fully testable sequential machines

CASCH: a scheduling algorithm for "high level"-synthesis

Functional abstraction of logic gates for switch-level simulation

LAST: a Layout Area and Shape function esTimator for high level applications

A new decomposition method for multilevel circuit design

Translating system specifications to VHDL

A framework for hierarchical performance analysis

PHIDEO: a silicon compiler for high speed algorithms

Design of a persistent programming environment in an object oriented language using clustering and composite objects

DONALD: a workbench for interactive design space exploration and sizing of analog circuits

Structure based methods for parallel pattern fault simulation in combinational circuits

Iterative compaction: an improved approach to graph and circuit bisection

A fast and efficient algorithm for determining fanout trees in large networks

Hybrid compiled/interpreted simulation of MOS circuits

Module synthesis for finite state machines

Correct interactive transformational synthesis of DSP hardware

An approach to design flow management in CAD frameworks

Synthesis of multi-level logic with one symbolic input

A probabilistic fault model for analog faults

Electrical modelling of lossy on-chip multilevel interconnecting lines

Datapath optimization using feedback

Circuit partitioning for waveform relaxation

SHARP-looking geometric partitioning

Formal method for self-timed design

On the selection of a partial scan path with respect to target faults

A global router for sea-of-gates circuits

A hierarchical approach to timing verification in CMOS VLSI design

MACHETE: synthesis of sequential machines for easy testability

Specification of timing constraints for controller synthesis

Incremental switch-level simulation with zero/integer-delay

Efficient shape curve construction in floorplan design

Decomposing data machines

Formal methods for silicon compilation

HERESY: a hybrid approach to automatic schematic generation

Affine transformations for multi-dimensional signal processing on ASIC regular arrays

A hardware design system based on object-oriented principles

A new approach to layout of custom analog cells

Experiments with autonomous test of PLAs

On L × n boolean matrices with all L × k submatrices having $2^{k}$ distinct row vectors

Optimization techniques for multiple output function synthesis

Periodic signal suppression in a concurrent fault simulator

Verification of synthesized circuits at register transfer level with flow graphs

Why to incorporate a data definition language into a CAD frameworks extension language

PLATO: a CAD tool for logic synthesis based on decomposition

The automatic diagnosis of faults in analogue and mixed-signal circuits

Restructuring VLSI layout representations for efficiency

Performance macromodelling and optimization of regular VLSI structures

Partitioning a network into n pieces with a time-efficient net cost function

Array folding using heuristics and simulated annealing

Model-based fault diagnosis of sequential circuits and its acceleration

Mickey: a macro cell global router

Clock independent timing verification of level-sensitive latches

Testability analysis of hierarchical finite state machines

On probabilistic switch-level simulation for asynchronous circuits

Goal oriented slicing enumeration through shape function clipping

Data flow graphs: system specification with the most unrestricted semantics

GRTL: a graphical platform for pipelined system design

Design by similarity using transaction modeling and statistical techniques

Interactive symbolic distortion analysis of analogue integrated circuits

A self-checking PLA automatic generator tool based on unordered codes encoding

A proposed hardware fault simulation engine

Proceedings of the conference on European design automation (EURO-DAC '91)

Content Provider	ACM Digital Library
Editor	Ambler, Tony De Man, Hugo Jess, Jochen
Copyright Year	1991
Abstract	Welcome to EDAC 91 in Amsterdam, the second event of a series that hopefully will develop towards the focal point in the area of design automation on European soil. We thank fellow professionals all over the world who responded so well to the first event in Glasgow, and we thank the 120 volunteers who, under the experienced guidance of Hugo De Man, evaluated the 241 submitted contributions and helped us in the putting together of the EDAC 91 programme. There are many other people who contributed to the preparations of EDAC 91 and whose names should be mentioned - too many1 Let me select Tatsuo Ohtsuki who, in addition to finding the best referees from Japan for paper evaluation, persuaded Hitoshi Watanabe to contribute to our opening session as a keynote speaker; or Raul Camposano for doing a great job in finding top notch referees in the USA. Let's mention Dave Storey, last year's Finance Chairman who, together with Gordon Adshead, successfully went through the tedious process of closing the books of EDAC 90, for us to know what the financial platform for EDAC 91 would be. Lots of credits go to Tracy Eglin, CEP's good spirit of EDAC 91, for putting up with everybody's (and particularly my) temper.Perhaps Paul Weil of ACMISIGDA should be explicitly given credit for operating as a negotiator with the US professional societies about all kinds of issues concerning sponsorship and 'in-cooperation' status. It is no longer a secret that that the US-DAC is concerned about EDAC's appearance as the European "Design Automation Conference". That is why this year (according to a proposal by Laurel Kaleda from the IEEE Computer Society) we have called EDAC the 'European Conference on Design Automation' - in case you may not have noticed that little change. Anyway, there will be some discussing and diplomatic activity around those issues in the coming months. As a result of that there may be some changes in policy in the near future. Whatever the result of all this is, EDAC shall continue to exist as the European forum devoted to design automation as a research item and a business activity. It will pursue its course, determined to integrate the various movements that are emerging in Europe with or without support from abroad. We are convinced that the integration of various efforts in Europe is an item of primary importance as the current scenario shows too much diversity. The coordination with the US and Japan is in focus. At the end of the line we envisage a set of yearly events in the US, the Far East and Europe that cooperate and are complementary at the same time.The RAI in Amsterdam gives us a little more space that the Glasgow site, enabling us to put the trade show into the centre of the conference activity, so the vendors may feel more comfortable this year. Depending on the success of this set-up we may allow the vendor activity to grow even more. Whatever the case may be, EDAC in any future form is going to consider a top quality technical programme to be the central event of the conference.Another item we absolutely feel committed to is to keep the European flavour of the conference - more than that, to develop a style of conference that captures the unique features of European research in front of a truly universal background. If DAC wants its trade show to move across the ocean to show in Europe, that is fine. However, it will have to function as an ingredient of a 'European' meal. It is going to be the exotic spice of US DA business on top of a European industrial structure that functions completely differently and has it own genuine dynamics.Everyone involved in setting up EDAC 91 sincerely hopes that you will enjoy the event. All of us will be eager to learn from you as to how we may improve the event. Give us your ideas. EDAC will need many volunteers in the future and perhaps you will find it worthwhile to contribute to its organisation in one way or another. Do not hesitate to talk to any of the organising committee members in Amsterdam.
ISBN	0818621303
Language	English
Publisher	IEEE Computer Society Press
Publisher Date	1991-02-25
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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