NDLI: Proceedings of the 14th international symposium on Systems synthesis (ISSS '01)

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A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems

Powering networks on chips: energy-efficient and reliable interconnect design for SoCs

Retargetable static timing analysis for embedded software

RTL semantics and methodology

New design paradigms: what needs to be standardized?

Loop fusion for memory space optimization

An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling

Static resource models of instruction sets

Embedded systems technologies for application-specific architecture platforms

Programming models for network processors

Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults

Accelerating boolean satisfiability through application specific processing

Exploiting scratch-pad memory using Presburger formulas

Performance analysis with confidence intervals for embedded software processes

SystemC: a modeling platform supporting multiple design abstractions

Cache-efficient memory layout of aggregate data structures

Current consumption dynamics at instruction and program level for a VLIW DSP processor

Combined instruction and loop parallelism in array synthesis for FPGAs

System design of a telecommunication router

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques

Considering power variations of DVS processing elements for energy minimisation in distributed systems

System-level interconnect architecture exploration for custom memory organizations

On-line fault detection in a hardware/software co-design environment: system partitioning

The standard SpecC language

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

Dynamic modeling of inter-instruction effects for execution time estimation

Conditional speculation and its effects on performance and area for high-level snthesis

Network processing in content inspection applications

High-level automatic pipelining for sequential circuits

Functional abstraction driven design space exploration of heterogeneous programmable architectures

An optimal memory allocation for application-specific multiprocessor system-on-chip

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Interoperability as a design issue in C++ based modeling environments

Data cache energy minimizations through programmable tag size matching to the applications

System level optimization and design space exploration for low power

A data scheduler for multi-context reconfigurable architectures

Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines

Modeling and simulation of steady state and transient behaviors for emergent SoCs

APEX: access pattern based memory architecture exploration

Design and simulation of a pipelined decompression architecture for embedded systems

Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design

Phase coupled operation assignment for VLIW processors with distributed register files

Efficient instruction-level optimization methodology for low-power embedded systems

Scheduling and partitioning for multiple loop nests

Soft-cores generation by instruction set analysis

Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS

Source code transformation based on software cost analysis

Object oriented hardware synthesis and verification

Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design

Control and communication performance analysis of embedded DSP systems in the MASIC methodology

Application of Software design patterns to DSP library design

Proceedings of the 14th international symposium on Systems synthesis (ISSS '01)

Content Provider	ACM Digital Library
Editor	Benini, L. Aboulhamid, El Mostapha Hermida, Roman Jacome, M. Wu, A. Miranda, M. Madsen, J. Jerraya, A. A. Camposano, R. Knight, J. Rosenstiel, W. Mavaddat, F.
Copyright Year	2001
Abstract	On behalf of the ISSS 2001 Steering and Technical Program committees, I would like to welcome you to Montréal and to The International Symposium on System Synthesis (ISSS). ISSS is a major international forum presenting emerging techniques for the system-level design and synthesis of computing systems. Having begun as the International Workshop on High-Level Synthesis in the mid-80's, it attracts leading design automation professionals from around the world.ISSS 2001 is the 14th in this very successful series of symposia. This year, in addition to regular presentations, the Symposium includes invited talks by leading industrial and academic experts covering emerging network processor technologies, new paradigms designs and perspectives in System-on-a-Chip as well as two discussion panels. To encourage discussion among the Symposium participants, each technical session will consist of oral presentations followed by a poster session where the authors of presented papers will answer any further questions and provide additional details of their works. This year technical sessions cover the following topics.1. System-Level Synthesis2. Hardware-Software Co-Design3. Programmable (Multi-)Processor-Based Design and Synthesis4. System Design Experience and Methodologies5. Embedded and Real-Time System Software6. High-Level and Architectural Synthesis7. Co-design of Distributed and multiprocessor architectures8. Synthesis for Low Power, Testability and Verifiability in the above areas.
Related Links	http://www.isss-symposium.com
ISBN	1581134185
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-09-30
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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