NDLI: Proceedings of the 13th international symposium on System synthesis (ISSS '00)

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FDRA: a software-pipelining algorithm for embedded VLIW processors

Architectures for one billion of transistors

Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis system

Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures

Intervals in software execution cost analysis

Embedded Java

Lower bound estimation for low power high-level synthesis

Low power storage cycle budget distribution tool support for hierarchical graphs

YAML: a tool for hardware design visualization and capture

Battery-driven dynamic power management of portable systems

Instruction scheduling for clustered VLIW architectures

Execution condition analysis in high level synthesis: a unified approach

Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations

A Transformational approach to constraint relaxation of a time-driven simulation model

Code generation for embedded processors

A multi-level strategy for software power estimation

Mapping array communication onto FIFO communication - towards an implementation

The nimber compiler for agile hardware: a research platform

The power managing OS meets a thermally aware processor

Scheduling coarse-grain operations for VLIW processors

Efficient hardware controller synthesis for synchronous dataflow graph in system level design

Systematic data reuse exploration methodology for irregular access patterns

Embedded systems verification with FGPA-enhanced in-circuit emulator

Source code optimization and profiling of energy consumption in embedded systems

Hardware synthesis from SPDF representation for multimedia applications

Compiler optimization on instruction scheduling for low power

Efficient integration of behavioral synthesis within existing design flows

Conditional scheduling for embedded systems using genetic list scheduling

Verification of embedded systems using a petri net based representation

Experiments with the peripheral virtual component interface

A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct

SDL as a system level specification language for application-specific hardware in a rapid prototyping environment

Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation

Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

Proceedings of the 13th international symposium on System synthesis (ISSS '00)

Content Provider	ACM Digital Library
Editor	MacMillen, Don Jacome, Margarida Hermida, Román Rau, Bob Feldmann, P. de Jong, G. Catthoor, F. Benini, Luca Sciuto, Donatella Tirado, Francisco Wolf, W. Najjar, Walid Dutt, Nikil Kurdahi, Fadi Eles, Petru De Micheli, G. Marwedel, Peter MacMillen, D. Verkest, Diederik
Copyright Year	2000
Abstract	As the accelerated progress of electronic technology pushes the integration of more and more complex systems on a single chip, and promotes the combination of sophisticated hardware and software components to achieve very high levels of performance at decreasing costs, system designers are permanently committed to devising new ways of merging automation and abstraction techniques to deal with this complexity, and obtain competitive designs in shorter times. In this challenging scenario the International Symposium on System Synthesis has been serving, during the last fifteen years, as a forum of reference for discussion of the latest developments in system level design methodologies and tools.Having begun as the High-Level Synthesis Workshop in 1984, ISSS has reached maturity by continually promoting the interaction between academic and industrial agents, and widening its scope to include emerging topics in system design. ISSS 2000, the $13^{th}$ edition of this successful series of symposia, includes the following topics: System-level synthesis Hardware-software co-design Programmable (multi-) processor-based design and synthesis System design experience and methodologies Embedded and real-time system software High-level and architectural synthesis Synthesis for low power, testability and verifiability in the above areas This year we have received 61 paper submissions coming from 19 different countries, which consolidates the tradition of ISSS as a truly international event. All the submission and review processes were fully electronic. Based on the result of the first round of the review process, where each paper was sent to at least five independent reviewers, a first selection of "clearly accepted" and "clearly rejected" papers was made. All the remaining papers were further debated in two subsequent rounds until a consensus on the selection of 18 high quality papers was finally reached. Also based on quality criteria the Program Committee decided to include six additional papers as short presentations.ISSS 2000 also features three special sessions with invited talks that have been organized by leading experts from academia (Giovanni De Micheli, Donatella Sciuto) and industry (Don MacMillen). In addition, two embedded tutorials organized by Peter Marwedel and Mateo Valero, and a panel session on the trends and achievements in system level design, have been programmed.
ISBN	1581132670
Language	English
Publisher	IEEE Computer Society
Publisher Date	2000-09-20
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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