NDLI: Soft-cores generation by instruction set analysis

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A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems

Powering networks on chips: energy-efficient and reliable interconnect design for SoCs

Retargetable static timing analysis for embedded software

RTL semantics and methodology

New design paradigms: what needs to be standardized?

Loop fusion for memory space optimization

An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling

Static resource models of instruction sets

Embedded systems technologies for application-specific architecture platforms

Programming models for network processors

Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults

Accelerating boolean satisfiability through application specific processing

Exploiting scratch-pad memory using Presburger formulas

Performance analysis with confidence intervals for embedded software processes

SystemC: a modeling platform supporting multiple design abstractions

Cache-efficient memory layout of aggregate data structures

Current consumption dynamics at instruction and program level for a VLIW DSP processor

Combined instruction and loop parallelism in array synthesis for FPGAs

System design of a telecommunication router

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques

Considering power variations of DVS processing elements for energy minimisation in distributed systems

System-level interconnect architecture exploration for custom memory organizations

On-line fault detection in a hardware/software co-design environment: system partitioning

The standard SpecC language

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

Dynamic modeling of inter-instruction effects for execution time estimation

Conditional speculation and its effects on performance and area for high-level snthesis

Network processing in content inspection applications

High-level automatic pipelining for sequential circuits

Functional abstraction driven design space exploration of heterogeneous programmable architectures

An optimal memory allocation for application-specific multiprocessor system-on-chip

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Interoperability as a design issue in C++ based modeling environments

Data cache energy minimizations through programmable tag size matching to the applications

System level optimization and design space exploration for low power

A data scheduler for multi-context reconfigurable architectures

Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines

Modeling and simulation of steady state and transient behaviors for emergent SoCs

APEX: access pattern based memory architecture exploration

Design and simulation of a pipelined decompression architecture for embedded systems

Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design

Phase coupled operation assignment for VLIW processors with distributed register files

Efficient instruction-level optimization methodology for low-power embedded systems

Scheduling and partitioning for multiple loop nests

Soft-cores generation by instruction set analysis

Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS

Source code transformation based on software cost analysis

Object oriented hardware synthesis and verification

Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design

Control and communication performance analysis of embedded DSP systems in the MASIC methodology

Application of Software design patterns to DSP library design

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