NDLI: Nanowire-aware routing considering high cut mask complexity

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A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems

Evaluation of functional mock-up interface for vehicle power network modeling

System simulation from operational data

New game, new goal posts: a recent history of timing closure

Walking a thin line: performance and quality grading vs. yield overcut

Energy efficient MapReduce with VFI-enabled multicore platforms

Complementary communication path for energy efficient on-chip optical interconnects

On-chip interconnection network for accelerator-rich architectures

Bandwidth-efficient on-chip interconnect designs for GPGPUs

DimNoC: a dim silicon approach towards power-efficient on-chip network

Domain-wall memory buffer for low-energy NoCs

An EDA framework for large scale hybrid neuromorphic computing systems

Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system

A spiking neuromorphic design with resistive crossbar

Vortex: variation-aware training for memristor X-bar

Jump test for metallic CNTs in CNFET-based SRAM

A reconfigurable analog substrate for highly efficient maximum flow computation

Robust design of E/E architecture component platforms

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory

Area and performance co-optimization for domain wall memory in application-specific embedded systems

Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM

Interleaved multi-bank scratchpad memories: a probabilistic description of access conflicts

PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory

Guidelines to design parity protected write-back L1 data cache

Construction of reconfigurable clock trees for MCMM designs

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction

Routing-architecture-aware analytical placement for heterogeneous FPGAs

PARR: pin access planning and regular routing for self-aligned double patterning

Local search algorithms for timing-driven placement under arbitrary delay models

3DIC benefit estimation and implementation guidance from 2DIC implementation

DERA: yet another differential fault attack on cryptographic devices based on error rate analysis

Vibration-based secure side channel for medical devices

Information leakage chaff: feeding red herrings to side channel attackers

TyTAN: tiny trust anchor for tiny devices

Memory heat map: anomaly detection in real-time embedded systems using memory behavior

Compacting privacy-preserving k-nearest neighbor search using logic synthesis

Battery lifetime-aware automotive climate control for electric vehicles

Security analysis of automotive architectures using probabilistic model checking

Security aware network controllers for next generation automotive embedded systems

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification

Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling

Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communication

Nautilus: fast automated IP design space search using guided genetic algorithms

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures

Acceleration of control flows on reconfigurable architecture with a composite method

GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing

Trends in functional verification: a 2014 industry study

Verifying SystemC using stateful symbolic simulation

In-circuit temporal monitors for runtime verification of reconfigurable designs

Sequential equivalence checking of clock-gated circuits

Verification of gate-level arithmetic circuits by function extraction

Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles

Security and privacy challenges in industrial internet of things

Blocking unsafe behaviors in control systems through static and dynamic policy enforcement

Timing-aware control software design for automotive systems

Compositional modeling and analysis of automotive feature product lines

The challenge of interoperability: model-based integration for automotive control software

Introduction to stochastic computing and its challenges

An introduction into fault-tolerant quantum computing

Design automation challenges for scalable quantum architectures

A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms

Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks

Domain wall memory based digital signal processors for area and energy-efficiency

DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design

Scalable-effort classifiers for energy-efficient machine learning

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias

High performance dummy fill insertion with coupling and uniformity constraints

An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT

Effective model-based mask fracturing for mask cost reduction

HAFIX: hardware-assisted flow integrity extension

Performance analysis of a memristive crossbar PUF design

Adaptive characterization and emulation of delay-based physical unclonable functions using statistical models

Self-correcting STTRAM under magnetic field attacks

On using control signals for word-level identification in a gate-level netlist

Efficient dynamic information flow tracking on a processor with core debug interface

What don't we know about CPS architectures?

Design tool chain for cyber-physical systems: lessons learned

Models, abstractions, and architectures: the missing links in cyber-physical systems

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications

Revisiting accelerator-rich CMPs: challenges and solutions

SuperNet: multimode interconnect architecture for manycore chips

A low latency generic accuracy configurable adder

A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction

Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory

Understanding soft errors in uncore components

Interconnect reliability modeling and analysis for multi-branch interconnect trees

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

Novel power grid reduction method based on L1 regularization

A statistical methodology for noise sensor placement and full-chip voltage map generation

Cloning your mind: security challenges in cognitive system designs and their solutions

Design and verification for transportation system security

Impact assessment of net metering on smart home cyberattack detection

Ensuring functional safety compliance for ISO 26262

Automating design-space exploration: optimal deployment of automotive SW-components in an ISO26262 context

Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI

EnAAM: energy-efficient anti-aging for on-chip video memories

Mitigating the impact of faults in unreliable memories for error-resilient applications

A STT-RAM-based low-power hybrid register file for GPGPUs

Joint precision optimization and high level synthesis for approximate computing

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units

ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platforms

HARS: a heterogeneity-aware runtime system for self-adaptive multithreaded applications

Accelerating real-time embedded scene labeling with convolutional networks

SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs

Optimizing stream program performance on CGRA-based systems

Detecting hardware trojans using backside optical imaging of embedded watermarks

Detecting malicious modifications of data in third-party intellectual property cores

A practical circuit fingerprinting method utilizing observability don't care conditions

Investigation of obfuscation-based anti-reverse engineering for printed circuit boards

Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks

Highly efficient entropy extraction for true random number generators on FPGAs

Design & verification of automotive SoC firmware

Model-based testing of automotive software: some challenges and solutions

New trends in dark silicon

Approximate computing and the quest for computing efficiency

Core vs. uncore: the heart of darkness

A generic representation of CCSL time constraints for UML/MARTE models

Improving worst-case cache performance through selective bypassing and register-indexed cache

PACO: fast average-performance estimation for time-randomized caches

Increasing confidence on measurement-based contention bounds for real-time round-robin buses

Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration

Efficient design space exploration of embedded platforms

One-pass logic synthesis for graphene-based Pass-XNOR logic circuits

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions

Scalable sequence-constrained retention register minimization in power gating design

Equivalence among stochastic logic circuits and its application

Randomness meets feedback: stochastic implementation of logistic map dynamical system

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC

Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation

Evaluating battery aging on mobile devices

Design for low test pattern counts

Generation of close-to-functional broadside tests with equal primary input vectors

Nanowire-aware routing considering high cut mask complexity

Optimizing data placement for reducing shift operations on domain wall memories

A SPICE model of flexible transition metal dichalcogenide field-effect transistors

Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping

PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips

Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design

SoC security architecture: current practices and emerging needs

Pre-silicon security verification and validation: a formal perspective

Correctness and security at odds: post-silicon validation of modern SoC designs

Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehicles

Formal methods for semi-autonomous driving

Integrated power management in IoT devices under wide dynamic ranges of operation

Ambient energy harvesting nonvolatile processors: from circuit to system

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling

Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters

Including variability of physical models into the design automation of cyber-physical systems

PASS: priority assignment of real-time tasks with dynamic suspending behavior under fixed-priority scheduling

Resource usage templates and signatures for COTS multicore processors

Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systems

Area-efficient pipelining for FPGA-targeted high-level synthesis

CMOST: a system-level FPGA compilation framework

Avoiding transitional effects in dynamic circuit specialisation on FPGAs

Efficient memory partitioning for parallel data access in multidimensional arrays

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

Physically aware high level synthesis design flow

An algorithmic framework for efficient large-scale circuit simulation using exponential integrators

Variation aware cross-talk aggressor alignment by mixed integer linear programming

TA-FTA: transition-aware functional timing analysis with a four-valued encoding

An efficient algorithm for statistical timing yield optimization

Criticality-dependency-aware timing characterization and analysis

A timing graph based approach to mode merging

Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits

mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process

Towards enhancing analog circuits sizing using SMT-based techniques

Verifying inevitability of phase-locking in a charge pump phase lock loop using sum of squares programming

Adaptive compressed sensing architecture in wireless brain-computer interface

A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space

The SIMON and SPECK lightweight block ciphers

EM attack sensor: concept, circuit, and design-automation methodology

Design and integration challenges of building security hardware IP

Achieving power and reliability sign-off for automotive semiconductor designs

Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips

Hayat: harnessing dark silicon and variability for aging deceleration and balancing

Network footprint reduction through data access and computation placement in NoC-based manycores

Designing time partitions for real-time hypervisor with sufficient temporal independence

Compiler directed automatic stack trimming for efficient non-volatile processors

Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor

Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems

Parallel circuit simulation using the direct method on a heterogeneous cloud

An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form

Design tools for oscillator-based computing systems

Layout-dependent-effects-aware analytical analog placement

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography

To collect or not to collect: just-in-time garbage collection for high-performance SSDs with long lifetimes

Achieving SLC performance with MLC flash memory

Virtual flash chips: rethinking the layer design of flash devices to improve data recoverability

FlexLevel: a novel NAND flash storage system design for LDPC latency reduction

Approximate storage for energy efficient spintronic memories

A synthesis methodology for application-specific logic-in-memory designs

Pushing multiple patterning in sub-10nm: are we ready?

EUV and e-beam manufacturability: challenges and solutions

Layout optimization and template pattern verification for directed self-assembly (DSA)

Virtual to the (near) end: using virtual platforms for continuous integration

Power-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCs

An Analysis of Accelerator Coupling in Heterogeneous Architectures

A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's

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