NDLI: PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory

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PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory

Content Provider	ACM Digital Library
Author	Melhem, Rami Jones, Alex Seyedzadeh, Seyed Mohammad Maddah, Rakan
Abstract	Nonvolatile memory technologies such as Phase Change Memory (PCM) and Spin-Transfer Torque Random Access Memory (STT-RAM) are emerging as promising replacements to DRAM. Before deploying STT-RAM and PCM into functional systems, a number of challenges still remain. Specifically, both require relatively high write energy, STT-RAM suffers from high bit error rates and PCM suffers from low endurance. A common solution to overcome those challenges is to minimize the number of bits changed per write. In this work, we introduce Pseudo-Random Encoding Scheme (PRES) to minimize the number of bit changes during memory writes. PRES maps the write data vector into an intermediate highly random set of data vectors. Subsequently, the intermediate data vector that yields the least number of differences when compared to the currently stored data is selected. Our evaluation shows that PRES reduces bit flips by up to 25% over a baseline differential writing scheme. Further, PRES reduces bit flips by 15% over the leading bit-flip minimization scheme, while decreasing encoding and decoding complexities by more than 90%.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450335201
DOI	10.1145/2744769.2755440
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-06-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Memory Endurance Pseudo-random encoding
Content Type	Text
Resource Type	Article

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