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| Content Provider | ACM Digital Library |
|---|---|
| Author | Nurvitadhi, Eriko Melber, Joseph Fleming, Kermin Hoe, James C. Wang, Yu Weisz, Gabriel |
| Abstract | The advent of FPGA acceleration platforms with direct coherent access to processor memory creates an opportunity for accelerating applications with irregular parallelism governed by large in-memory pointer-based data structures. This paper uses the simple reference behavior of a linked-list traversal as a proxy to study the performance potentials of accelerating these applications on shared-memory processor-FPGA systems. The linked-list traversal is parameterized by node layout in memory, per-node data payload size, payload dependence, and traversal concurrency to capture the main performance effects of different pointer-based data structures and algorithms. The paper explores the trade-offs over a wide range of implementation options available on shared-memory processor-FPGA architectures, including using tightly-coupled processor assistance. We make observations of the key effects on currently available systems including the Xilinx Zynq, the Intel QuickAssist QPI FPGA Platform, and the Convey HC-2. The key results show: (1) the FPGA fabric is least efficient when traversing a single list with non-sequential node layout and a small payload size; (2) processor assistance can help alleviate this shortcoming; and (3) when appropriate, a fabric only approach that interleaves multiple linked list traversals is an effective way to maximize traversal performance. |
| Starting Page | 264 |
| Ending Page | 273 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781450338561 |
| DOI | 10.1145/2847263.2847269 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2016-02-21 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Cache coherence Heterogeneous systems Fpga Pointer chasing Shared memory |
| Content Type | Text |
| Resource Type | Article |
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