NDLI: PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems

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PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems

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PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems

Content Provider	ACM Digital Library
Author	Kumar, Akash Nguyen, Tuan D.A.
Abstract	Partial reconfiguration (PR) is gaining more attention from the research community because of its flexibility in dynamically changing some parts of the system at runtime. However, the current PR tools need the designer's involvement in manually specifying the shapes and locations for the PR regions (PRRs). It requires not only deep knowledge of the FPGA device, the system architecture, but also many trial-and-error attempts to find the best-possible floorplan. Therefore, many research works have been conducted to propose automatic floorplanners for PR systems. However, one of the most significant limitations of those works is that they only consider the PRRs and ignore all other static modules. In this paper, we propose a novel PR floorplanner called PRFloor. It takes into account all components in the system. The main ideas behind PRFloor are the unique recursive pseudo-bipartitioning heuristic using a new, simple, yet effective Nonlinear Integer Programming-based bipartitioner. The PRFloor performs very well in the experiments with various synthetic PR system setups with up to 130 modules, 24 PRRs and 85% of the FPGA resource. The average maximum clock frequency obtained for the actual PR systems implemented using PRFloor is even 3% higher than the similar systems without PR capability.
Starting Page	149
Ending Page	158
Page Count	10
File Format	PDF
ISBN	9781450338561
DOI	10.1145/2847263.2847270
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-02-21
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Partial reconfiguration Nlp Fpga floorplan Bipartition
Content Type	Text
Resource Type	Article

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