NDLI: Pre-bond testable low-power clock tree design for 3D stacked ICs

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Pre-bond testable low-power clock tree design for 3D stacked ICs

Content Provider	ACM Digital Library
Author	Zhao, Xin Lim, Sung Kyu Lee, Hsien-Hsin S. Lewis, Dean L.
Abstract	Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3D clock tree design. First, each die needs a complete 2D clock tree for the pre-bond testing. In addition, the entire 3D stack needs a complete 3D clock tree for post-bond testing and normal operations. In the case of two-die stack, a straightforward solution is to have two complete 2D clock trees connected with a single Through-Silicon-Via (TSV). We show that this solution suffers from long wirelength and high clock power consumption. Instead, our algorithm minimizes the overall wirelength and clock power consumption while providing the pre-bond testability and post-bond operability under given skew and slew constraints. Compared with the single-TSV solution, SPICE simulation results show that our multi-TSV approach significantly reduces the clock power by up to 15.9% for two-die and 29.7% for four-die stack. In addition, the wirelength reduction is up to 24.4% and 42.0%.
Starting Page	184
Ending Page	190
Page Count	7
File Format	PDF
ISBN	9781605588001
DOI	10.1145/1687399.1687433
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-11-02
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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