NDLI: Yield estimation of SRAM circuits using "Virtual SRAM Fab"

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Yield estimation of SRAM circuits using "Virtual SRAM Fab"

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Yield estimation of SRAM circuits using "Virtual SRAM Fab"

Content Provider	ACM Digital Library
Author	Heng, Fook-Luen Singh, Rama N. Mukhopadhyay, Saibal Das, Koushik K. Acar, Emrah Kanj, Rouwaida N. Lee, Jin-Fuw Nassif, Sani Bansal, Aditya Kim, Keunwoo Singhee, Amith Chuang, Ching-Te
Abstract	Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as "Virtual SRAM Fab", for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32-22nm technology nodes.
Starting Page	631
Ending Page	636
Page Count	6
File Format	PDF
ISBN	9781605588001
DOI	10.1145/1687399.1687516
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-11-02
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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