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  1. Proceedings of the 2006 workshop on Memory system performance and correctness (MSPC '06)
  2. Keynote talk challenges in chip multiprocessor memory systems
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Deconstructing process isolation
Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures
Keynote talk challenges in chip multiprocessor memory systems
What do high-level memory models mean for transactions?
A flexible data to L2 cache mapping approach for future multicore processors
Reliability-aware data placement for partial memory protection in embedded processors
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
Memory models for open-nested transactions
A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems
Smarter garbage collection with simplifiers
Implicit and explicit optimizations for stencil computations
Atomicity via source-to-source translation

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Keynote talk challenges in chip multiprocessor memory systems

Content Provider ACM Digital Library
Author Wood, David A.
Abstract The semiconductor industry appears on the brink of an arms race, competing to see which company can cram the most cores on a single die. Yet early entries are hardly well-balanced, general-purpose computers: Sun's Niagara has feeble floating-point performance and IBM's Cell processor is a thinly disguised GPU. Worse, no company has announced anything that will help address the real problem: programming the multithreaded applications needed to exploit the ample computational resources. This talk will discuss several challenges facing the memory system designers of emerging computation-rich chip multiprocessors.
Starting Page 61
Ending Page 61
Page Count 1
File Format PDF
ISBN 1595935789
DOI 10.1145/1178597.1178607
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2006-10-22
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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