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  1. Proceedings of the 2006 workshop on Memory system performance and correctness (MSPC '06)
  2. Reliability-aware data placement for partial memory protection in embedded processors
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Deconstructing process isolation
Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures
Keynote talk challenges in chip multiprocessor memory systems
What do high-level memory models mean for transactions?
A flexible data to L2 cache mapping approach for future multicore processors
Reliability-aware data placement for partial memory protection in embedded processors
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
Memory models for open-nested transactions
A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems
Smarter garbage collection with simplifiers
Implicit and explicit optimizations for stencil computations
Atomicity via source-to-source translation

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Reliability-aware data placement for partial memory protection in embedded processors

Content Provider ACM Digital Library
Author Austin, Todd Mehrara, Mojtaba
Abstract Low cost protection of embedded systems against soft errors has recently become a major concern. This issue is even more critical in memory elements that are inherently more prone to transient faults. In this paper, we propose a reliability aware data placement technique in order to partially protect embedded memory systems. We show that by adopting this method instead of traditional placement schemes with complete memory protection, an acceptable level of fault tolerance can be achieved while incurring less area and power overhead. In this approach, each variable in the program is placed in either protected or non-protected memory area according to the profile-driven liveness analysis of all memory variables. In order to measure the level of fault coverage, we inject faults into the memory during the course of program execution in a Monte Carlo simulation framework. Subsequently, we calculate the coverage of partial protection scheme based on the number of protected, failed and crashed runs during the fault injection experiment.
Starting Page 11
Ending Page 18
Page Count 8
File Format PDF
ISBN 1595935789
DOI 10.1145/1178597.1178600
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2006-10-22
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Embedded systems Partial memory protection Selective data placement Memory lifetime Soft errors
Content Type Text
Resource Type Article
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