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  1. Proceedings of the 2006 workshop on Memory system performance and correctness (MSPC '06)
  2. Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
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Deconstructing process isolation
Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures
Keynote talk challenges in chip multiprocessor memory systems
What do high-level memory models mean for transactions?
A flexible data to L2 cache mapping approach for future multicore processors
Reliability-aware data placement for partial memory protection in embedded processors
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
Memory models for open-nested transactions
A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems
Smarter garbage collection with simplifiers
Implicit and explicit optimizations for stencil computations
Atomicity via source-to-source translation

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Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms

Content Provider ACM Digital Library
Author Adams, Michael D. Wise, David S.
Abstract A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by• time• TLB misses• L1 misses• L2 misses• paging to disk• scaling on distributed processors, and• portability to multiple platforms.It provides a philosophy and tools that allow the programmer to deal with the memory hierarchy invisibly, from L1 and L2 to TLB, paging, and interprocessor communication. Used together, they provide a cache-oblivious style of programming.Plots are presented to support these claims on an implementation of Cholesky factorization crafted directly from the paradigm in C with a few intrinsic calls. The results in this paper focus on low-level performance, including the new Morton-hybrid representation to take advantage of hardware and compiler optimizations. In particular, this code beats Intel's Matrix Kernel Library and matches AMD's Core Math Library, losing a bit on L1 misses while winning decisively on TLB-misses.
Starting Page 41
Ending Page 50
Page Count 10
File Format PDF
ISBN 1595935789
DOI 10.1145/1178597.1178604
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2006-10-22
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Morton-hybrid Paging Quadtrees Parallel processing Tlb Cache misses Cholesky factorization
Content Type Text
Resource Type Article
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