NDLI: Architecture validation for processors

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Volume 23, Issue 5, Dec. 1995

Volume 23, Issue 4, Sept. 1995

Volume 23, Issue 3, June 1995

Volume 23, Issue 2, May 1995

The MIT Alewife machine

The EM-X parallel computer

The SPLASH-2 programs

Efficient strategies for software-only protocols in shared-memory multiprocessors

Dynamic self-invalidation

Boosting the performance of hybrid snooping cache protocols

Destage algorithms for disk arrays with non-volatile caches

Evaluating multi-port frame buffer designs for a mesh-connected multicomputer

Are crossbars really dead?

Exploring configurations of functional units in an out-of-order superscalar processor

Unconstrained speculative execution with predicated state buffering

A comparison of full and partial predicated execution support for ILP processors

Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor

Performance evaluation of the PowerPC 620 microarchitecture

Reducing TLB and memory overhead using online superpage promotion

Speeding up irregular applications in shared-memory multiprocessors

An efficient, fully adaptive deadlock recovery scheme

Analysis and implementation of hybrid switching

Configurable flow control mechanisms for fault-tolerant routing

Vector multiprocessors with arbitrated memory access

Design of cache memories for multi-threaded dataflow architecture

Skewed associativity enhances performance predictability

A comparative analysis of schemes for correlated branch prediction

Next cache line and set prediction

A comparison of architectural support for messaging in the TMC CM-5 and the Cray T3D

Optimizing memory system performance for communication in parallel computers

Empirical evaluation of the CRAY-T3D

Optimization of instruction fetch mechanisms for high issue rates

Instruction fetching

Instruction cache fetch policies for speculative execution

Streamlining data cache access with fast address calculation

CAT—caching address tags

Simultaneous multithreading

Architecture validation for processors

Multiscalar processors

Volume 23, Issue 1, March 1995

Architecture validation for processors

Content Provider	ACM Digital Library
Author	Dill, David L. Horowitz, Mark A. Yang, C. Han Ho, Richard C.
Abstract	Modem, high performance microprocessors are extremely complex machines which require substantial validation effort to ensure functional correctness prior to tapeout. Generating the corner cases to test these designs is a mostly manual process, where completion is hard to judge. Experience shows that the errors that are caught late in the design, many post-silicon, are interactions between different components in very improbable corner case situations. In this paper we present a technique that targets such error-causing interactions by automatically generat- ing test vectors that will cause the processor to exercise all transitions of the control logic in simulation. We use techniques from formal verification to derive transition tours of a fully enumerated state graph of the control logic of the processor. Our system works from a Verilog description of the original machine and is currently being used to validate an embedded dual-issue processor in the node controller of the Stanford FLASH Multiprocessor. Modeling the processor control results in 200K states and an 8M instruction trace to check all transitions of control arcs.
Starting Page	404
Ending Page	413
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/225830.224450
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	23
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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