NDLI: Configurable flow control mechanisms for fault-tolerant routing

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The MIT Alewife machine

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The SPLASH-2 programs

Efficient strategies for software-only protocols in shared-memory multiprocessors

Dynamic self-invalidation

Boosting the performance of hybrid snooping cache protocols

Destage algorithms for disk arrays with non-volatile caches

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Are crossbars really dead?

Exploring configurations of functional units in an out-of-order superscalar processor

Unconstrained speculative execution with predicated state buffering

A comparison of full and partial predicated execution support for ILP processors

Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor

Performance evaluation of the PowerPC 620 microarchitecture

Reducing TLB and memory overhead using online superpage promotion

Speeding up irregular applications in shared-memory multiprocessors

An efficient, fully adaptive deadlock recovery scheme

Analysis and implementation of hybrid switching

Configurable flow control mechanisms for fault-tolerant routing

Vector multiprocessors with arbitrated memory access

Design of cache memories for multi-threaded dataflow architecture

Skewed associativity enhances performance predictability

A comparative analysis of schemes for correlated branch prediction

Next cache line and set prediction

A comparison of architectural support for messaging in the TMC CM-5 and the Cray T3D

Optimizing memory system performance for communication in parallel computers

Empirical evaluation of the CRAY-T3D

Optimization of instruction fetch mechanisms for high issue rates

Instruction fetching

Instruction cache fetch policies for speculative execution

Streamlining data cache access with fast address calculation

CAT—caching address tags

Simultaneous multithreading

Architecture validation for processors

Multiscalar processors

Volume 23, Issue 1, March 1995

Configurable flow control mechanisms for fault-tolerant routing

Content Provider	ACM Digital Library
Author	Dao, Binh Vien Yalamanchili, Sudhakar Duato, Jose
Abstract	Fault-tolerant routing protocols in modern interconnection networks rely heavily on the network flow control mechanisms used. Optimistic flow control mechanisms such as wormhole routing (WR) realize very good performance, but are prone to deadlock in the presence of faults. Conservative flow control mechanisms such as pipelined circuit switching (PCS) insures existence of a path to the destination prior to message transmission, but incurs increased overhead. Existing fault-tolerant routing protocols are designed with one or the other, and must accommodate their associated constraints. This paper proposes the use of configurable flow control mechanisms. Routing protocols can then be designed such that in the vicinity of faults, protocols use a more conservative flow control mechanism, while the majority of messages that traverse fault-free portions of the network utilize a WR like flow control to maximize performance. Such protocols are referred to as two-phase protocols, where routing decisions are provided some control over the operation of the virtual channels. This ability provides new avenues for optimizing message passing performance in the presence of faults. A fully adaptive two-phase protocol is proposed and compared via simulation to those based on WR and PCS. The architecture of a network router supporting configurable flow control is described, and the paper concludes with avenues for future research.
Starting Page	220
Ending Page	229
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/225830.224433
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	23
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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