NDLI: Destage algorithms for disk arrays with non-volatile caches

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The MIT Alewife machine

The EM-X parallel computer

The SPLASH-2 programs

Efficient strategies for software-only protocols in shared-memory multiprocessors

Dynamic self-invalidation

Boosting the performance of hybrid snooping cache protocols

Destage algorithms for disk arrays with non-volatile caches

Evaluating multi-port frame buffer designs for a mesh-connected multicomputer

Are crossbars really dead?

Exploring configurations of functional units in an out-of-order superscalar processor

Unconstrained speculative execution with predicated state buffering

A comparison of full and partial predicated execution support for ILP processors

Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor

Performance evaluation of the PowerPC 620 microarchitecture

Reducing TLB and memory overhead using online superpage promotion

Speeding up irregular applications in shared-memory multiprocessors

An efficient, fully adaptive deadlock recovery scheme

Analysis and implementation of hybrid switching

Configurable flow control mechanisms for fault-tolerant routing

Vector multiprocessors with arbitrated memory access

Design of cache memories for multi-threaded dataflow architecture

Skewed associativity enhances performance predictability

A comparative analysis of schemes for correlated branch prediction

Next cache line and set prediction

A comparison of architectural support for messaging in the TMC CM-5 and the Cray T3D

Optimizing memory system performance for communication in parallel computers

Empirical evaluation of the CRAY-T3D

Optimization of instruction fetch mechanisms for high issue rates

Instruction fetching

Instruction cache fetch policies for speculative execution

Streamlining data cache access with fast address calculation

CAT—caching address tags

Simultaneous multithreading

Architecture validation for processors

Multiscalar processors

Volume 23, Issue 1, March 1995

Destage algorithms for disk arrays with non-volatile caches

Content Provider	ACM Digital Library
Author	Jacobson, Quinn Varma, Anujan
Abstract	In a disk array with a nonvolatile write cache, destages from the cache to the disk are performed in the background asynchronously while read requests from the host system are serviced in the foreground. In this paper, we study a number of algorithms for scheduling destages in a RAID-5 system. We introduce a new scheduling algorithm, called linear threshold scheduling, that adaptively varies the rate of destages to disks based on the instantaneous occupancy of the write cache. The performance of the algorithm is compared with that of a number of alternative scheduling approaches such as least-cost scheduling and high/low mark. The algorithms are evaluated in terms of their effectiveness in making destages transparent to the servicing of read requests from the host, disk utilization, and their ability to tolerate bursts in the workload without causing an overflow of the write cache. Our results show that linear threshold scheduling provides the best read performance of all the algorithms compared, while still maintaining a high degree of burst tolerance. An approximate implementation of the linear-threshold scheduling algorithm is also described. The approximate algorithm can be implemented with much lower overhead, yet its performance is virtually identical to that of the ideal algorithm.
Starting Page	83
Ending Page	95
Page Count	13
File Format	PDF
ISSN	01635964
DOI	10.1145/225830.224042
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	23
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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