NDLI: VM-based shared memory on low-latency, remote-memory-access networks

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Volume 25, Issue 5, Dec. 1997

Volume 25, Issue 4, Sept. 1997

Volume 25, Issue 3, June 1997

Volume 25, Issue 2, May 1997

Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences

Exploiting instruction level parallelism in processors by caching scheduled groups

On deadlocks in interconnection networks

Implementing multidestination worms in switch-based parallel systems

Tolerating multiple failures in RAID architectures with optimal storage and uniform declustering

Hardware fault containment in scalable shared-memory multiprocessors

Effects of communication latency, overhead, and bandwidth in a cluster architecture

The Mercury Interconnect Architecture

The design and analysis of a cache architecture for texture mapping

Designing high bandwidth on-chip caches

Memory-system design considerations for dynamically-scheduled processors

The interaction of software prefetching with ILP processors in shared-memory systems

VM-based shared memory on low-latency, remote-memory-access networks

Efficient synchronization

Dynamic speculation and synchronization of data dependences

Dynamic instruction reuse

Complexity-effective superscalar processors

Coherence controller architectures for SMP-based CC-NUMA multiprocessors

Prefetching using Markov predictors

Data prefetching on the HP PA-8000

Target prediction for indirect jumps

The agree predictor

Trading conflict and capacity aliasing in conditional branch predictors

A language for describing predictors and its application to automatic synthesis

Run-time adaptive cache hierarchy management via reference analysis

The energy efficiency of IRAM architectures

DataScalar architectures

Volume 25, Issue 1, March 1997

VM-based shared memory on low-latency, remote-memory-access networks

Content Provider	ACM Digital Library
Author	Hunt, Galen Hardavellas, Nikolaos Cierniak, Michał Dwarkadas, Sandhya Stets, Robert Kontothanassis, Leonidas Scott, Michael Parthasarathy, Srinivasan Meira, Wagner
Abstract	Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such networks on the implementation and performance of software DSM. Specifically, we compare two DSM systems---Cashmere and TreadMarks---on a 32-processor DEC Alpha cluster connected by a Memory Channel network.Both Cashmere and TreadMarks use virtual memory to maintain coherence on pages, and both use lazy, multi-writer release consistency. The systems differ dramatically, however, in the mechanisms used to track sharing information and to collect and merge concurrent updates to a page, with the result that Cashmere communicates much more frequently, and at a much finer grain.Our principal conclusion is that low-latency networks make DSM based on fine-grain communication competitive with more coarse-grain approaches, but that further hardware improvements will be needed before such systems can provide consistently superior performance. In our experiments, Cashmere scales slightly better than TreadMarks for applications with false sharing. At the same time, it is severely constrained by limitations of the current Memory Channel hardware. In general, performance is better for TreadMarks.
Starting Page	157
Ending Page	169
Page Count	13
File Format	PDF
ISSN	01635964
DOI	10.1145/384286.264163
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	25
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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