NDLI: Memory-system design considerations for dynamically-scheduled processors

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Volume 25, Issue 5, Dec. 1997

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Volume 25, Issue 3, June 1997

Volume 25, Issue 2, May 1997

Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences

Exploiting instruction level parallelism in processors by caching scheduled groups

On deadlocks in interconnection networks

Implementing multidestination worms in switch-based parallel systems

Tolerating multiple failures in RAID architectures with optimal storage and uniform declustering

Hardware fault containment in scalable shared-memory multiprocessors

Effects of communication latency, overhead, and bandwidth in a cluster architecture

The Mercury Interconnect Architecture

The design and analysis of a cache architecture for texture mapping

Designing high bandwidth on-chip caches

Memory-system design considerations for dynamically-scheduled processors

The interaction of software prefetching with ILP processors in shared-memory systems

VM-based shared memory on low-latency, remote-memory-access networks

Efficient synchronization

Dynamic speculation and synchronization of data dependences

Dynamic instruction reuse

Complexity-effective superscalar processors

Coherence controller architectures for SMP-based CC-NUMA multiprocessors

Prefetching using Markov predictors

Data prefetching on the HP PA-8000

Target prediction for indirect jumps

The agree predictor

Trading conflict and capacity aliasing in conditional branch predictors

A language for describing predictors and its application to automatic synthesis

Run-time adaptive cache hierarchy management via reference analysis

The energy efficiency of IRAM architectures

DataScalar architectures

Volume 25, Issue 1, March 1997

Memory-system design considerations for dynamically-scheduled processors

Content Provider	ACM Digital Library
Author	Farkas, Keith I. Chow, Paul Vranesic, Zvonko Jouppi, Norman P.
Abstract	In this paper, we identify performance trends and design relationships between the following components of the data memory hierarchy in a dynamically-scheduled processor: the register file, the lockup-free data cache, the stream buffers, and the interface between these components and the lower levels of the memory hierarchy. Similar performance was obtained from all systems having support for fewer than four in-flight misses, irrespective of the register-file size, the issue width of the processor, and the memory bandwidth. While providing support for more than four in-flight misses did increase system performance, the improvement was less than that obtained by increasing the number of registers. The addition of stream buffers to the investigated systems led to a significant performance increase, with the larger increases for systems having less in-flight-miss support, greater memory bandwidth, or more instruction issue capability. The performance of these systems was not significantly affected by the inclusion of traffic filters, dynamic-stride calculators, or the inclusion of the per-load non-unity stride-predictor and the incremental-prefetching techniques, which we introduce. However, the incremental prefetching technique reduces the bandwidth consumed by stream buffers by 50% without a significant impact on performance.
Starting Page	133
Ending Page	143
Page Count	11
File Format	PDF
ISSN	01635964
DOI	10.1145/384286.264156
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	25
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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