NDLI: Adaptive backoff synchronization techniques

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Volume 17, Issue 6, Dec. 1989

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Evaluating the performance of four snooping cache coherency protocols

Multi-level shared caching techniques for scalability in VMP-M/C

Design and performance of a coherent cache for parallel logic programming architectures

The Epsilon dataflow processor

An architecture of a dataflow single chip processor

Exploiting data parallelism in signal processing on a dataflow machine

Architectural mechanisms to support sparse vector processing

A dynamic storage scheme for conflict-free vector access

SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture

2-D SIMD algorithms in the perfect shuffle networks

Systematic hardware adaptation of systolic algorithms

Task migration in hypercube multiprocessors

Characteristics of performance-optimal multi-level cache hierarchies

Supporting reference and dirty bits in SPUR's virtual address cache

Inexpensive implementations of set-associativity

Organization and performance of a two-level virtual-real cache hierarchy

High performance communications in processor networks

Introducing memory into the switch elements of multiprocessor interconnection networks

Using feedback to control tree saturation in multistage interconnection networks

Constructing replicated systems using processors with point-to-point communication links

KCM: a knowledge crunching machine

A high performance Prolog processor with multiple function units

Evaluation of memory system for integrated Prolog processor IPP

A type driven hardware engine for Prolog clause retrieval over a large knowledge base

Comparing software and hardware schemes for reducing the cost of branches

Improving performance of small on-chip instruction caches

Achieving high instruction cache performance with an optimizing compiler

The impact of code density on instruction cache performance

Can dataflow subsume von Neumann computing?

Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results

Architectural and organizational tradeoffs in the design of the MultiTitan CPU

Run-time checking in Lisp by integrating memory addressing and range checking

Multiple vs. wide shared bus multiprocessors

Performance measurements on a commercial multiprocessor running parallel code

Interprocessor communication speed and performance in distributed-memory parallel processors

Analysis of computation-communication issues in dynamic dataflow architectures

Logic simulation on massively parallel architectures

R256: a research parallel processor for scientific computation

A three-port/three-access register file for concurrent processing and I/O communication in a RISC-like graphics engine

An architecture framework for application-specific and scalable architectures

Perfect Latin squares and parallel array access

An aperiodic storage scheme to reduce memory conflicts in vector processors

Analysis of vector access performance on skewed interleaved memory

Adaptive backoff synchronization techniques

A cache consistency protocol for multiprocessors with multistage networks

On data synchronization for multiprocessors

Volume 17, Issue 2, April 1989

Volume 17, Issue 1, March 1989

Adaptive backoff synchronization techniques

Content Provider	ACM Digital Library
Author	Agarwal, A. Cherian, M.
Abstract	Shared-memory multiprocessors commonly use shared variables for synchronization. Our simulations of real parallel applications show that large-scale cache-coherent multiprocessors suffer significant amounts of invalidation traffic due to synchronization. Large multiprocessors that do not cache synchronization variables are often more severely impacted. If this synchronization traffic is not reduced or managed adequately, synchronization references can cause severe congestion in the network. We propose a class of adaptive back-off methods that do not use any extra hardware and can significantly reduce the memory traffic to synchronization variables. These methods use synchronization state to reduce polling of synchronization variables. Our simulations show that when the number of processors participating in a barrier synchronization is small compared to the time of arrival of the processors, reductions of 20 percent to over 95 percent in synchronization traffic can be achieved at no extra cost. In other situations adaptive backoff techniques result in a tradeoff between reduced network accesses and increased processor idle time.
Starting Page	396
Ending Page	406
Page Count	11
File Format	PDF
ISSN	01635964
DOI	10.1145/74926.74970
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	17
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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