NDLI: Evaluation of memory system for integrated Prolog processor IPP

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Evaluating the performance of four snooping cache coherency protocols

Multi-level shared caching techniques for scalability in VMP-M/C

Design and performance of a coherent cache for parallel logic programming architectures

The Epsilon dataflow processor

An architecture of a dataflow single chip processor

Exploiting data parallelism in signal processing on a dataflow machine

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A dynamic storage scheme for conflict-free vector access

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Constructing replicated systems using processors with point-to-point communication links

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A high performance Prolog processor with multiple function units

Evaluation of memory system for integrated Prolog processor IPP

A type driven hardware engine for Prolog clause retrieval over a large knowledge base

Comparing software and hardware schemes for reducing the cost of branches

Improving performance of small on-chip instruction caches

Achieving high instruction cache performance with an optimizing compiler

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Can dataflow subsume von Neumann computing?

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Analysis of vector access performance on skewed interleaved memory

Adaptive backoff synchronization techniques

A cache consistency protocol for multiprocessors with multistage networks

On data synchronization for multiprocessors

Volume 17, Issue 2, April 1989

Volume 17, Issue 1, March 1989

Evaluation of memory system for integrated Prolog processor IPP

Content Provider	ACM Digital Library
Author	Yamaguchi, S. Bandoh, T. Morioka, M.
Abstract	This paper discusses an optimal memory system to realize a high performance integrated Prolog processor, the IPP. First, the memory access characteristics of Prolog are analyzed by a simulator, which simulates the execution of a Prolog program at a micro instruction level. The main findings from this analysis are that: the write access ratio of Prolog is larger than that of procedural languages; and performance improvement requires the memory system to process concentrated, large write accesses effectively.Then the Prolog acceleration strategies for conventional cache memories are discussed. Comparison is made of cache memories (store-swap, store-through) and a stack buffer, regarding not only performance but also reliability, complexity and effects on procedural languages. The advanced store-through cache with a multi-stage write buffer and an interleaved main memory are seen to have the same performance level as the store-swap cache. When considering data reliability, the advanced store-through cache is judged more suitable for the IPP than the store-swap cache. In a comparison between stack buffer and advanced store-through cache, the stack buffer is found to achieve higher peak performance, but this is affected by the program features. On the other hand, the advanced store-through cache constantly gets high performance for Prolog and procedural languages. As a result, it is concluded that the advanced store-through cache is best suited to the IPP.
Starting Page	203
Ending Page	210
Page Count	8
File Format	PDF
ISSN	01635964
DOI	10.1145/74926.74949
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	17
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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