NDLI: Introducing memory into the switch elements of multiprocessor interconnection networks

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Volume 17, Issue 6, Dec. 1989

Volume 17, Issue 5, Sep. 1989

Volume 17, Issue 4, June 1989

Volume 17, Issue 3, June 1989

Evaluating the performance of four snooping cache coherency protocols

Multi-level shared caching techniques for scalability in VMP-M/C

Design and performance of a coherent cache for parallel logic programming architectures

The Epsilon dataflow processor

An architecture of a dataflow single chip processor

Exploiting data parallelism in signal processing on a dataflow machine

Architectural mechanisms to support sparse vector processing

A dynamic storage scheme for conflict-free vector access

SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture

2-D SIMD algorithms in the perfect shuffle networks

Systematic hardware adaptation of systolic algorithms

Task migration in hypercube multiprocessors

Characteristics of performance-optimal multi-level cache hierarchies

Supporting reference and dirty bits in SPUR's virtual address cache

Inexpensive implementations of set-associativity

Organization and performance of a two-level virtual-real cache hierarchy

High performance communications in processor networks

Introducing memory into the switch elements of multiprocessor interconnection networks

Using feedback to control tree saturation in multistage interconnection networks

Constructing replicated systems using processors with point-to-point communication links

KCM: a knowledge crunching machine

A high performance Prolog processor with multiple function units

Evaluation of memory system for integrated Prolog processor IPP

A type driven hardware engine for Prolog clause retrieval over a large knowledge base

Comparing software and hardware schemes for reducing the cost of branches

Improving performance of small on-chip instruction caches

Achieving high instruction cache performance with an optimizing compiler

The impact of code density on instruction cache performance

Can dataflow subsume von Neumann computing?

Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results

Architectural and organizational tradeoffs in the design of the MultiTitan CPU

Run-time checking in Lisp by integrating memory addressing and range checking

Multiple vs. wide shared bus multiprocessors

Performance measurements on a commercial multiprocessor running parallel code

Interprocessor communication speed and performance in distributed-memory parallel processors

Analysis of computation-communication issues in dynamic dataflow architectures

Logic simulation on massively parallel architectures

R256: a research parallel processor for scientific computation

A three-port/three-access register file for concurrent processing and I/O communication in a RISC-like graphics engine

An architecture framework for application-specific and scalable architectures

Perfect Latin squares and parallel array access

An aperiodic storage scheme to reduce memory conflicts in vector processors

Analysis of vector access performance on skewed interleaved memory

Adaptive backoff synchronization techniques

A cache consistency protocol for multiprocessors with multistage networks

On data synchronization for multiprocessors

Volume 17, Issue 2, April 1989

Volume 17, Issue 1, March 1989

Introducing memory into the switch elements of multiprocessor interconnection networks

Content Provider	ACM Digital Library
Author	Baer, J. L. Mizrahi, H. E. Lazowska, E. D. Zahorjan, J.
Abstract	As VLSI technology continues to improve, circuit area is gradually being replaced by pin restrictions as the limiting factor in design. Thus, it is reasonable to anticipate that on-chip memory will become increasingly inexpensive since it is a simple, regular structure than can easily take advantage of higher densities.In this paper we examine one way in which this trend can be exploited to improve the performance of multistage interconnection networks (MINs). In particular, we consider the performance benefits of placing significant memory in each MIN switch. This memory is used in two ways: to store (the unique copies of) data items and to maintain directories. The data storage function allows data to be placed nearer processors that reference it relatively frequently, at the cost of increased distance to other processors. The directory function allows data items to migrate in reaction to changes in program locality. We call our MIN architecture the Memory Hierarchy Network (MHN).In a preliminary investigation of the merits of this design [8] we examined the performance of MHNs under the simplifying assumption that an unlimited amount of memory was available in each switch. We found that despite the longer switch processing times of the MHN, system performance is improved over simpler, conventional schemes based on caching.In this paper we refine the earlier model to account for practical storage limitations. We study ways to reduce the amount of directory storage required by keeping only partial information regarding the current location of data items. The price paid for this reduction in memory requirement is more complicated (and in some circumstances slower) protocols. We obtain comparative performance estimates in an environment containing a single global memory module and a tree-structured MIN. Our results indicate that the MHN organization can have substantial performance benefits and so should be of increasing interest as the enabling technology becomes available.
Starting Page	158
Ending Page	166
Page Count	9
File Format	PDF
ISSN	01635964
DOI	10.1145/74926.74944
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	17
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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