NDLI: Building timing predictable embedded systems

Content Provider	ACM Digital Library
Author	Rochange, Christine Grund, Daniel Wilhelm, Reinhard Falk, Heiko Axer, Philip Sebastian, Maurice Reineke, Jan Ernst, Rolf Girault, Alain Hanxleden, Reinhard Von Jonsson, Bengt Marwedel, Peter Guan, Nan Yi, Wang
Copyright Year	2014
Abstract	A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.
Starting Page	1
Ending Page	37
Page Count	37
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/2560033
Volume Number	13
Issue Number	4
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-03-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Embedded systems Predictability Resource sharing Safety-critical systems Timing analysis
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Predictable Framework for Safety-Critical Embedded Systems

Data cache locking for tight timing calculations

Schedulability analysis of EDF-scheduled embedded real-time systems with resource sharing

Critical embedded automotive networks

Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments

Component-based modeling and verification of dynamic adaptation in safety-critical embedded systems

A Deadline-Floor Inheritance Protocol for EDF Scheduled Embedded Real-Time Systems with Resource Sharing

Editorial: Schizoid Design for Critical Embedded Systems

PROARTIS: Probabilistically Analyzable Real-Time Systems

Building timing predictable embedded systems

Similar Documents

A Predictable Framework for Safety-Critical Embedded Systems

Data cache locking for tight timing calculations

Schedulability analysis of EDF-scheduled embedded real-time systems with resource sharing

Critical embedded automotive networks

Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments

Component-based modeling and verification of dynamic adaptation in safety-critical embedded systems

A Deadline-Floor Inheritance Protocol for EDF Scheduled Embedded Real-Time Systems with Resource Sharing

Editorial: Schizoid Design for Critical Embedded Systems

PROARTIS: Probabilistically Analyzable Real-Time Systems

Building timing predictable embedded systems