NDLI: Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

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Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

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Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

Content Provider	ACM Digital Library
Author	Belhaire, Eric Mazoyer, Pascale Chappert, Claude Zhao, Weisheng
Copyright Year	2009
Abstract	As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.
Starting Page	1
Ending Page	16
Page Count	16
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/1596543.1596548
Volume Number	9
Issue Number	2
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-10-29
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA MRAM System on Chip (SOC) Architecture Low power Multicontext Nonvolatile Runtime reconfiguration (RTR) Spin transfer torque (STT)
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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