NDLI: REDEFINE: Runtime reconfigurable polymorphic ASIC

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REDEFINE: Runtime reconfigurable polymorphic ASIC

Content Provider	ACM Digital Library
Author	Nandy, S. K. Narayan, Ranjani Chetia, Jugantor Das, Saptarsi Varadarajan, Keshavan Fell, Alexander Joseph, Nimmy Biswas, Prasenjit C., Ramesh Reddy Rao, Adarsh Alle, Mythri
Copyright Year	2009
Abstract	Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime $\textit{re}-composition.$ It is a “future-proof” custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16× in power and 8× in area when compared to an ASIC. REDEFINE implementation consumes 0.1× the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000× more than that of REDEFINE.
Starting Page	1
Ending Page	48
Page Count	48
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/1596543.1596545
Volume Number	9
Issue Number	2
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-10-29
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	NoC Polymorphic ASIC Application synthesis Custom instruction extension Dataflow software pipeline Honeycomb Router Runtime reconfiguration
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

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