NDLI: A self-tuning cache architecture for embedded systems

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ACM Transactions on Embedded Computing Systems (TECS) : Volume 16

ACM Transactions on Embedded Computing Systems (TECS) : Volume 15

ACM Transactions on Embedded Computing Systems (TECS) : Volume 14

ACM Transactions on Embedded Computing Systems (TECS) : Volume 13

ACM Transactions on Embedded Computing Systems (TECS) : Volume 12

ACM Transactions on Embedded Computing Systems (TECS) : Volume 11

ACM Transactions on Embedded Computing Systems (TECS) : Volume 11S

ACM Transactions on Embedded Computing Systems (TECS) : Volume 10

ACM Transactions on Embedded Computing Systems (TECS) : Volume 9

ACM Transactions on Embedded Computing Systems (TECS) : Volume 8

ACM Transactions on Embedded Computing Systems (TECS) : Volume 7

ACM Transactions on Embedded Computing Systems (TECS) : Volume 6

ACM Transactions on Embedded Computing Systems (TECS) : Volume 5

ACM Transactions on Embedded Computing Systems (TECS) : Volume 4

ACM Transactions on Embedded Computing Systems (TECS) : Volume 3

Issue 4, November 2004

Issue 3, August 2004

Issue 2, May 2004

Editorial: Special issue on dynamically adaptable embedded systems

An optimal algorithm for minimizing run-time reconfiguration delay

A design flow for partially reconfigurable hardware

Adaptive scheduling server for power-aware real-time tasks

Blocking-aware processor voltage scheduling for real-time tasks

Dynamic adaptation for fault tolerance and power management in embedded real-time systems

The design of dynamically reconfigurable datapath coprocessors

Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling

A self-tuning cache architecture for embedded systems

AIDA: Adaptive application-independent data aggregation in wireless sensor networks

Issue 1, February 2004

ACM Transactions on Embedded Computing Systems (TECS) : Volume 2

ACM Transactions on Embedded Computing Systems (TECS) : Volume 1

A self-tuning cache architecture for embedded systems

Content Provider	ACM Digital Library
Author	Lysecky, Roman Zhang, Chuanjun Vahid, Frank
Copyright Year	2004
Abstract	Memory accesses often account for about half of a microprocessor system's power consumption. Customizing a microprocessor cache's total size, line size, and associativity to a particular program is well known to have tremendous benefits for performance and power. Customizing caches has until recently been restricted to core-based flows, in which a new chip will be fabricated. However, several configurable cache architectures have been proposed recently for use in prefabricated microprocessor platforms. Tuning those caches to a program is still, however, a cumbersome task left for designers, assisted in part by recent computer-aided design (CAD) tuning aids. We propose to move that CAD on-chip, which can greatly increase the acceptance of tunable caches. We introduce on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program. Our heuristic seeks not only to reduce the number of configurations that must be examined, but also traverses the search space in a way that minimizes costly cache flushes. By simulating numerous Powerstone and MediaBench benchmarks, we show that such a dynamic self-tuning cache saves on average 40% of total memory access energy over a standard nontuned reference cache.
Starting Page	407
Ending Page	425
Page Count	19
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/993396.993405
Volume Number	3
Issue Number	2
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Cache Architecture tuning Configurable Dynamic optimization Embedded systems Low energy Low power On-chip CAD
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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