NDLI: Impact of Parallelism and Memory Architecture on FPGA Communication Energy

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

Issue 4(Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015), September 2016

A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing

FPGA-Based Dynamically Reconfigurable SQL Query Processing

Shared Memory Multicore MicroBlaze System with SMP Linux Support

ODoST: Automatic Hardware Acceleration for Biomedical Model Integration

Introduction

Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

Impact of Parallelism and Memory Architecture on FPGA Communication Energy

Fine-Grained Interconnect Synthesis

Issue 3(Special Issue on Reconfigurable Components with Source Code), September 2016

Issue 2(Special Section on RAW2014), February 2016

Issue 1(Special Section on the 2014 International Symposium on Applied Reconfigurable Computing), November 2015

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

Impact of Parallelism and Memory Architecture on FPGA Communication Energy

Content Provider	ACM Digital Library
Author	Lakata, David Dehon, André Kadric, Edin
Copyright Year	2016
Description	Author Affiliation: University of Pennsylvania, Philadelphia, PA(Dehon, Andr; Lakata, David; Kadric, Edin)
Abstract	The energy in FPGA computations is dominated by data communication energy, either in the form of memory references or data movement on interconnect. In this article, we explore how to use data placement and parallelism to reduce communication energy. We show that parallelism can reduce energy and that the optimal level of parallelism increases with the problem size. We further explore how FPGA memory architecture (memory block size(s), memory banking, and spacing between memory banks) can impact communication energy, and determine how to organize the memory architecture to guarantee that the energy overhead compared to the optimally matched architecture for the design is never more than 60%. We specifically show that an architecture with 32 bit wide, 16Kb internally banked memories placed every 8 columns of 10 4-LUT logic blocks is within 61% of the optimally matched architecture across the VTR 7 benchmark set and a set of parallelism-tunable benchmarks. Without internal banking, the worst-case overhead is 98%, achieved with an architecture with 32 bit wide, 8Kb memories placed every 9 columns, roughly comparable to the memory organization on the Cyclone V (where memories are placed about every 10 columns). Monolithic 32 bit wide, 16Kb memories placed every 10 columns (comparable to 18Kb and 20Kb memories used in Virtex 4 and Stratix V FPGAs) have a 180% worst-case energy overhead. Furthermore, we show practical cases where designs mapped for optimal parallelism use 4.7 × less energy than designs using a single processing element.
Starting Page	1
Ending Page	23
Page Count	23
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2857057
Volume Number	9
Issue Number	4
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-08-22
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA Architecture Banking Communication Energy Memory Power
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Impact of Memory Architecture on FPGA Energy Consumption

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices

Impact of data transformations on memory bank locality

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Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations

The impact of exploiting instruction-level parallelism on shared-memory multiprocessors

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

Impact of Parallelism and Memory Architecture on FPGA Communication Energy

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