NDLI: ODoST: Automatic Hardware Acceleration for Biomedical Model Integration

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

Issue 4(Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015), September 2016

A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing

FPGA-Based Dynamically Reconfigurable SQL Query Processing

Shared Memory Multicore MicroBlaze System with SMP Linux Support

ODoST: Automatic Hardware Acceleration for Biomedical Model Integration

Introduction

Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

Impact of Parallelism and Memory Architecture on FPGA Communication Energy

Fine-Grained Interconnect Synthesis

Issue 3(Special Issue on Reconfigurable Components with Source Code), September 2016

Issue 2(Special Section on RAW2014), February 2016

Issue 1(Special Section on the 2014 International Symposium on Applied Reconfigurable Computing), November 2015

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

ODoST: Automatic Hardware Acceleration for Biomedical Model Integration

Content Provider	ACM Digital Library
Author	Bradley, Chris Sinnen, Oliver Yu, Ting
Copyright Year	2016
Description	Author Affiliation: University of Auckland, Auckland, New Zealand(Sinnen, Oliver; Bradley, Chris; Yu, Ting)
Abstract	Dynamic biomedical systems are mathematically described by Ordinary Differential Equations (ODEs) and their solution is often one of the most computationally intensive parts in biomedical simulations. With high inherent parallelism, hardware acceleration based on Field-Programmable Gate Arrays (FPGAs) has great potential to increase the computational performance of the model simulations, while being very power-efficient. However, the manual hardware implementation is complex and time consuming. The advantages of FPGA designs can only be realised if there is a general solution to automate the process. In this article, we propose a domain-specific high-level synthesis tool called ODoST that automatically generates an FPGA-based Hardware Accelerator Module (HAM) from a high-level description. In this direct approach, ODE equations are directly mapped to processing pipelines without any intermediate architecture layer of processing elements. We evaluate the generated HAMs on real hardware based on their resource usage, processing speed, and power consumption, and compare them with CPUs and a GPU. The results show that FPGA implementations can achieve 15.3 times more speedup compared to a single core CPU solution and perform similarly to an auto-generated GPU solution, while the FPGA implementations can achieve 14.5 times more power efficiency than the CPU and 3.1 times compared to the $\textit{optimised}$ GPU solution. Improved speedups are foreseeable based on further optimisations.
Starting Page	1
Ending Page	24
Page Count	24
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2870639
Volume Number	9
Issue Number	4
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-08-11
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	High-performance reconfigurable computing Biomedical modeling High-level synthesis
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Compiling for reconfigurable computing: A survey

Achieving High Performance with FPGA-Based Computing

Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing

NCBI BLASTP on High-Performance Reconfigurable Computing Systems

Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems

Optimization of Shared High-Performance Reconfigurable Computing Resources

High Performance and Area Efficient Flexible DSP Datapath Synthesis

Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing

High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centers

ODoST: Automatic Hardware Acceleration for Biomedical Model Integration

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ODoST: Automatic Hardware Acceleration for Biomedical Model Integration