NDLI: LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies

Content Provider	ACM Digital Library
Author	Hijaz, Farrukh Devadas, Srinivas Kurian, George Shi, Qingchuan Khan, Omer
Copyright Year	2016
Description	Author Affiliation: Massachusetts Institute of Technology(Khan, Omer; University of connecticut, Storrs, CT (Shi, Qingchuan; University of connecticut (hijaz, Farrukh); Massachusetts institute of technology, Cambridge, MA (Devadas, Srinivas); Kurian, George))
Abstract	The trend of increasing the number of cores to achieve higher performance has challenged efficient management of on-chip data. Moreover, many emerging applications process massive amounts of data with varying degrees of locality. Therefore, exploiting locality to improve on-chip traffic and resource utilization is of fundamental importance. Conventional multicore cache management schemes either manage the private cache (L1) or the Last-Level Cache (LLC), while ignoring the other. We propose a holistic $\textit{locality-aware}$ cache hierarchy management protocol for large-scale multicores. The proposed scheme improves on-chip data access latency and energy consumption by intelligently bypassing cache line replication in the L1 caches, and/or intelligently replicating cache lines in the LLC. The approach relies on low overhead yet highly accurate in-hardware runtime classification of data locality at both L1 cache and the LLC. The decision to bypass L1 and/or replicate in LLC is then based on the measured reuse at the fine granularity of cache lines. The locality tracking mechanism is decoupled from the sharer tracking structures that cause scalability concerns in traditional cache coherence protocols. Moreover, the complexity of the protocol is low since no additional coherence states are created. However, the proposed classifier incurs a $5.6\textit{KB}$ per-core storage overhead. On a set of parallel benchmarks, the locality-aware protocol reduces average energy consumption by 26% and completion time by 16%, when compared to the state-of-the-art Reactive-NUCA multicore cache management scheme.
Starting Page	1
Ending Page	28
Page Count	28
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/2983632
Volume Number	13
Issue Number	4
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-11-15
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Multicore Cache Locality
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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