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  1. Transactions on Architecture and Code Optimization (TACO)
  2. ACM Transactions on Architecture and Code Optimization (TACO) : Volume 1
  3. Issue 4, December 2004
  4. Toward kilo-instruction processors
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ACM Transactions on Architecture and Code Optimization (TACO) : Volume 13
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 12
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 11
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 10
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 9
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 8
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 7
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 6
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 5
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 4
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 3
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 2
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 1
Issue 4, December 2004
The optimum pipeline depth considering both power and performance
Toward kilo-instruction processors
An analysis of a resource efficient checkpoint architecture
Tolerating memory latency through push prefetching for pointer-intensive applications
Issue 3, September 2004
Issue 2, June 2004
Issue 1, March 2004

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Toward kilo-instruction processors

Content Provider ACM Digital Library
Author Santana, Oliverio J. Martínez, José F. Valero, Mateo Cristal, Adrián
Copyright Year 2004
Abstract The continuously increasing gap between processor and memory speeds is a serious limitation to the performance achievable by future microprocessors. Currently, processors tolerate long-latency memory operations largely by maintaining a high number of in-flight instructions. In the future, this may require supporting many hundreds, or even thousands, of in-flight instructions. Unfortunately, the traditional approach of scaling up critical processor structures to provide such support is impractical at these levels, due to area, power, and cycle time constraints.In this paper we show that, in order to overcome this resource-scalability problem, the way in which critical processor resources are managed must be changed. Instead of simply upsizing the processor structures, we propose a smarter use of the available resources, supported by a selective checkpointing mechanism. This mechanism allows instructions to commit out of order, and makes a reorder buffer unnecessary. We present a set of techniques such as multilevel instruction queues, late allocation and early release of registers, and early release of load/store queue entries. All together, these techniques constitute what we call a kilo-instruction processor, an architecture that can support thousands of in-flight instructions, and thus may achieve high performance even in the presence of large memory access latencies.
Starting Page 389
Ending Page 417
Page Count 29
File Format PDF
ISSN 15443566
e-ISSN 15443973
DOI 10.1145/1044823.1044825
Volume Number 1
Issue Number 4
Journal ACM Transactions on Architecture and Code Optimization (TACO)
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2004-12-01
Publisher Place New York
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword Memory wall Instruction-level parallelism Kilo-instruction processors Multicheckpointing
Content Type Text
Resource Type Article
Subject Hardware and Architecture Information Systems Software
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